libc: arm: fix setjmp abi non-conformance
As per the arm Procedure Call Standard for the Arm Architecture section 6.1.2 [1], VFP registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls. The current setjmp/longjmp implementations preserve only the core registers, with the jump buffer size too small to store the required co-processor registers. In accordance with the C Library ABI for the Arm Architecture section 6.11 [2], this patch sets _JBTYPE to long long adjusting _JBLEN to 20. It also emits vfp load/store instructions depending on architectural support, predicated at compile time on ACLE feature-test macros. [1] https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst [2] https://github.com/ARM-software/abi-aa/blob/main/clibabi32/clibabi32.rst
This commit is contained in:
Victor L. Do Nascimento
Richard Earnshaw
parent
90236c3a2c
commit
15ad816ddd
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@ -762,7 +762,7 @@ SUCH DAMAGE.
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(35) - Arm Ltd
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Copyright (c) 2009-2018 Arm Ltd
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Copyright (c) 2009-2022 Arm Ltd
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -12,9 +12,13 @@ _BEGIN_STD_C
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#if defined(__arm__) || defined(__thumb__)
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/*
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* All callee preserved registers:
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* v1 - v7, fp, ip, sp, lr, f4, f5, f6, f7
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* core registers:
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* r4 - r10, fp, sp, lr
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* VFP registers (architectural support dependent):
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* d8 - d15
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*/
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#define _JBLEN 23
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#define _JBLEN 20
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#define _JBTYPE long long
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#endif
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#if defined(__aarch64__)
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@ -27,34 +27,34 @@
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The interworking scheme expects functions to use a BX instruction
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to return control to their parent. Since we need this code to work
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in both interworked and non-interworked environments as well as with
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older processors which do not have the BX instruction we do the
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older processors which do not have the BX instruction we do the
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following:
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Test the return address.
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If the bottom bit is clear perform an "old style" function exit.
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(We know that we are in ARM mode and returning to an ARM mode caller).
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Otherwise use the BX instruction to perform the function exit.
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We know that we will never attempt to perform the BX instruction on
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an older processor, because that kind of processor will never be
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interworked, and a return address with the bottom bit set will never
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We know that we will never attempt to perform the BX instruction on
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an older processor, because that kind of processor will never be
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interworked, and a return address with the bottom bit set will never
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be generated.
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In addition, we do not actually assemble the BX instruction as this would
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require us to tell the assembler that the processor is an ARM7TDMI and
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it would store this information in the binary. We want this binary to be
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able to be linked with binaries compiled for older processors however, so
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we do not want such information stored there.
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we do not want such information stored there.
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If we are running using the APCS-26 convention however, then we never
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test the bottom bit, because this is part of the processor status.
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Instead we just do a normal return, since we know that we cannot be
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test the bottom bit, because this is part of the processor status.
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Instead we just do a normal return, since we know that we cannot be
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returning to a Thumb caller - the Thumb does not support APCS-26.
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Function entry is much simpler. If we are compiling for the Thumb we
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Function entry is much simpler. If we are compiling for the Thumb we
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just switch into ARM mode and then drop through into the rest of the
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function. The function exit code will take care of the restore to
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Thumb mode.
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For Thumb-2 do everything in Thumb mode. */
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.syntax unified
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@ -115,15 +115,15 @@ SYM (longjmp):
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#else
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#define RET tst lr, #1; \
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moveq pc, lr ; \
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.word 0xe12fff1e /* bx lr */
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.inst 0xe12fff1e /* bx lr */
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#endif
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#ifdef __thumb2__
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.macro COND where when
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.macro COND where when
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i\where \when
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.endm
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#else
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.macro COND where when
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.macro COND where when
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.endm
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#endif
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@ -140,7 +140,7 @@ SYM (longjmp):
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.macro PROLOGUE name
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.code 16
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bx pc
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nop
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nop
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.code 32
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SYM (.arm_start_of.\name):
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.endm
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@ -149,7 +149,7 @@ SYM (.arm_start_of.\name):
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.macro PROLOGUE name
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.endm
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#endif
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.macro FUNC_START name
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.text
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.align 2
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@ -164,61 +164,65 @@ SYM (\name):
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RET
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SIZE (\name)
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.endm
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/* --------------------------------------------------------------------
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int setjmp (jmp_buf);
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int setjmp (jmp_buf);
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-------------------------------------------------------------------- */
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FUNC_START setjmp
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/* Save all the callee-preserved registers into the jump buffer. */
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#ifdef __thumb2__
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mov ip, sp
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stmea a1!, { v1-v7, fp, ip, lr }
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stmia r0!, { r4-r10, fp, ip, lr }
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#else
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stmea a1!, { v1-v7, fp, ip, sp, lr }
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stmia r0!, { r4-r10, fp, sp, lr }
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#endif
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#if defined __ARM_FP || defined __ARM_FEATURE_MVE
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vstm r0, { d8-d15 }
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#endif
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#if 0 /* Simulator does not cope with FP instructions yet. */
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#ifndef __SOFTFP__
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/* Save the floating point registers. */
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sfmea f4, 4, [a1]
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#endif
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#endif
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#endif
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/* When setting up the jump buffer return 0. */
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mov a1, #0
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mov r0, #0
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FUNC_END setjmp
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/* --------------------------------------------------------------------
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volatile void longjmp (jmp_buf, int);
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-------------------------------------------------------------------- */
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FUNC_START longjmp
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/* If we have stack extension code it ought to be handled here. */
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/* Restore the registers, retrieving the state when setjmp() was called. */
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#ifdef __thumb2__
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ldmfd a1!, { v1-v7, fp, ip, lr }
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ldmia r0!, { r4-r10, fp, ip, lr }
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mov sp, ip
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#else
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ldmfd a1!, { v1-v7, fp, ip, sp, lr }
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ldmia r0!, { r4-r10, fp, sp, lr }
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#endif
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#if defined __ARM_FP || defined __ARM_FEATURE_MVE
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vldm r0, { d8-d15 }
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#endif
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#if 0 /* Simulator does not cope with FP instructions yet. */
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#ifndef __SOFTFP__
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/* Restore floating point registers as well. */
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lfmfd f4, 4, [a1]
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#endif
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#endif
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/* Put the return value into the integer result register.
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But if it is zero then return 1 instead. */
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movs a1, a2
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#ifdef __thumb2__
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it eq
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#endif
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moveq a1, #1
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/* Put the return value into the integer result register.
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But if it is zero then return 1 instead. */
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movs r0, r1
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it eq
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moveq r0, #1
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FUNC_END longjmp
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#endif
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