include/opcode/
* mips.h (mips_operand_type, mips_reg_operand_type): New enums. (mips_operand, mips_int_operand, mips_mapped_int_operand) (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) (mips_pcrel_operand): New structures. (mips_insert_operand, mips_extract_operand, mips_signed_operand) (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. (decode_mips_operand, decode_micromips_operand): Declare. opcodes/ * mips-formats.h: New file. * mips-opc.c: Include mips-formats.h. (reg_0_map): New static array. (decode_mips_operand): New function. * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) (int_c_map): New static arrays. (decode_micromips_operand): New function. * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (print_reg): New function. (mips_print_arg_state): New structure. (init_print_arg_state, print_insn_arg): New functions. (print_insn_args): Change interface and use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips): ...here. Update the call to print_insn_args. (print_insn_micromips): Use print_insn_args. gas/ * config/tc-mips.c (validate_mips_insn): Move further up file. Add insn_bits and decode_operand arguments. Use the mips_operand fields to work out which bits an operand occupies. Detect double definitions. (validate_micromips_insn): Move further up file. Call into validate_mips_insn.
This commit is contained in:
Richard Sandiford
parent
ca25afceea
commit
ac96b15958
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@ -1,3 +1,13 @@
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
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(mips_operand, mips_int_operand, mips_mapped_int_operand)
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(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
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(mips_pcrel_operand): New structures.
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(mips_insert_operand, mips_extract_operand, mips_signed_operand)
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(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
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(decode_mips_operand, decode_micromips_operand): Declare.
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h: Document MIPS16 "I" opcode.
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@ -332,6 +332,292 @@
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#define OP_SH_EVAOFFSET 7
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#define OP_MASK_EVAOFFSET 0x1ff
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/* Enumerates the various types of MIPS operand. */
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enum mips_operand_type {
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/* Described by mips_int_operand. */
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OP_INT,
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/* Described by mips_mapped_int_operand. */
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OP_MAPPED_INT,
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/* Described by mips_msb_operand. */
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OP_MSB,
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/* Described by mips_reg_operand. */
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OP_REG,
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/* Described by mips_reg_pair_operand. */
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OP_REG_PAIR,
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/* Described by mips_pcrel_operand. */
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OP_PCREL,
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/* A performance register. The field is 5 bits in size, but the supported
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values are much more restricted. */
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OP_PERF_REG,
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/* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
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as a normal 9-bit signed offset that is multiplied by four, but there
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are four special cases:
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-2 * 4 => -258 * 4
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-1 * 4 => -257 * 4
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0 * 4 => 256 * 4
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1 * 4 => 257 * 4. */
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OP_ADDIUSP_INT,
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/* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
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5-bit register fields, both of which must be set to the destination
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register. */
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OP_CLO_CLZ_DEST,
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/* A register list for a microMIPS LWM or SWM instruction. The operand
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size determines whether the 16-bit or 32-bit encoding is required. */
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OP_LWM_SWM_LIST,
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/* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
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V Meaning
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----- -------
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0EEE0 8 copies of $vN[E], OB format
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0EE01 4 copies of $vN[E], QH format
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10110 all 8 elements of $vN, OB format
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10101 all 4 elements of $vN, QH format
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11110 8 copies of immediate N, OB format
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11101 4 copies of immediate N, QH format. */
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OP_MDMX_IMM_REG,
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/* A register operand that must match the destination register. */
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OP_REPEAT_DEST_REG,
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/* A register operand that must match the previous register. */
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OP_REPEAT_PREV_REG,
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/* $pc, which has no encoding in the architectural instruction. */
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OP_PC
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};
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/* Enumerates the types of MIPS register. */
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enum mips_reg_operand_type {
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/* General registers $0-$31. Software names like $at can also be used. */
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OP_REG_GP,
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/* Floating-point registers $f0-$f31. */
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OP_REG_FP,
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/* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
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can also be written $fcc0-$fcc7. */
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OP_REG_CCC,
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/* FPRs used in a vector capacity. They can be written $f0-$f31
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or $v0-$v31, although the latter form is not used for the VR5400
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vector instructions. */
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OP_REG_VEC,
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/* DSP accumulator registers $ac0-$ac3. */
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OP_REG_ACC,
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/* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
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also be used in some contexts. */
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OP_REG_COPRO,
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/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
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also be used in some contexts. */
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OP_REG_HW
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};
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/* Base class for all operands. */
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struct mips_operand
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{
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/* The type of the operand. */
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enum mips_operand_type type;
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/* The operand occupies SIZE bits of the instruction, starting at LSB. */
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unsigned short size;
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unsigned short lsb;
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};
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/* Describes an integer operand with a regular encoding pattern. */
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struct mips_int_operand
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{
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struct mips_operand root;
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/* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
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The cyclically previous field value encodes 1 << SHIFT less than that,
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and so on. E.g.
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- for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
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but 15 encodes -1.
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- { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
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shifted left two places.
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- { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
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that 0 encodes 8.
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- { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
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unsigned int max_val;
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int bias;
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unsigned int shift;
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/* True if the operand should be printed as hex rather than decimal. */
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bfd_boolean print_hex;
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};
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/* Uses a lookup table to describe a small integer operand. */
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struct mips_mapped_int_operand
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{
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struct mips_operand root;
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/* Maps each encoding value to the integer that it represents. */
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const int *int_map;
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/* True if the operand should be printed as hex rather than decimal. */
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bfd_boolean print_hex;
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};
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/* An operand that encodes the most significant bit position of a bitfield.
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Given a bitfield that spans bits [MSB, LSB], some operands of this type
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encode MSB directly while others encode MSB - LSB. Each operand of this
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type is preceded by an integer operand that specifies LSB.
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The assembly form varies between instructions. For some instructions,
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such as EXT, the operand is written as the bitfield size. For others,
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such as EXTS, it is written in raw MSB - LSB form. */
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struct mips_msb_operand
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{
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struct mips_operand root;
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/* The assembly-level operand encoded by a field value of 0. */
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int bias;
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/* True if the operand encodes MSB directly, false if it encodes
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MSB - LSB. */
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bfd_boolean add_lsb;
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/* The maximum value of MSB + 1. */
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unsigned int opsize;
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};
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/* Describes a single register operand. */
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struct mips_reg_operand
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{
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struct mips_operand root;
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/* The type of register. */
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enum mips_reg_operand_type reg_type;
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/* If nonnull, REG_MAP[N] gives the register associated with encoding N,
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otherwise the encoding is the same as the register number. */
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const unsigned char *reg_map;
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};
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/* Describes an operand that encodes a pair of registers. */
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struct mips_reg_pair_operand
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{
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struct mips_operand root;
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/* The type of register. */
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enum mips_reg_operand_type reg_type;
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/* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
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unsigned char *reg1_map;
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unsigned char *reg2_map;
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};
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/* Describes an operand that is calculated relative to a base PC.
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The base PC is usually the address of the following instruction,
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but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
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struct mips_pcrel_operand
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{
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struct mips_operand root;
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/* The low ALIGN_LOG2 bits of the base PC are cleared to give PC'. */
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unsigned int align_log2 : 8;
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/* The operand is shifted left SHIFT places and added to PC'.
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The operand is signed if IS_SIGNED. */
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unsigned int shift : 8;
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unsigned int is_signed : 1;
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/* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
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reinstated. This is true for jumps and branches and false for
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PC-relative data instructions. */
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unsigned int include_isa_bit : 1;
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/* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
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This is true for JALX and false otherwise. */
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unsigned int flip_isa_bit : 1;
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};
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/* Return a version of INSN in which the field specified by OPERAND
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has value UVAL. */
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static inline unsigned int
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mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
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unsigned int uval)
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{
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unsigned int mask;
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mask = (1 << operand->size) - 1;
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insn &= ~(mask << operand->lsb);
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insn |= (uval & mask) << operand->lsb;
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return insn;
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}
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/* Extract OPERAND from instruction INSN. */
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static inline unsigned int
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mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
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{
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return (insn >> operand->lsb) & ((1 << operand->size) - 1);
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}
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/* UVAL is the value encoded by OPERAND. Return it in signed form. */
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static inline int
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mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
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{
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unsigned int sign_bit, mask;
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mask = (1 << operand->size) - 1;
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sign_bit = 1 << (operand->size - 1);
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return ((uval + sign_bit) & mask) - sign_bit;
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}
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/* Return the integer that OPERAND encodes as UVAL. */
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static inline int
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mips_decode_int_operand (const struct mips_int_operand *operand,
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unsigned int uval)
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{
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uval |= (operand->max_val - uval) & -(1 << operand->root.size);
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uval += operand->bias;
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uval <<= operand->shift;
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return uval;
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}
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/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
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Return the address that it encodes. */
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static inline bfd_vma
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mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
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bfd_vma base_pc, unsigned int uval)
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{
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bfd_vma addr;
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addr = base_pc & -(1 << operand->align_log2);
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if (operand->is_signed)
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addr += mips_signed_operand (&operand->root, uval) * (1 << operand->shift);
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else
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addr += uval << operand->shift;
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if (operand->include_isa_bit)
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addr |= base_pc & 1;
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if (operand->flip_isa_bit)
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addr ^= 1;
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return addr;
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}
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/* This structure holds information for a particular instruction. */
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struct mips_opcode
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@ -1215,6 +1501,7 @@ enum
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Many instructions are short hand for other instructions (i.e., The
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jal <register> instruction is short for jalr <register>). */
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extern const struct mips_operand *decode_mips_operand (const char *);
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extern const struct mips_opcode mips_builtin_opcodes[];
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extern const int bfd_mips_num_builtin_opcodes;
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extern struct mips_opcode *mips_opcodes;
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@ -1780,6 +2067,7 @@ extern const int bfd_mips16_num_opcodes;
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" bcdefghij lmn pq st xyz"
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*/
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extern const struct mips_operand *decode_micromips_operand (const char *);
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extern const struct mips_opcode micromips_opcodes[];
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extern const int bfd_micromips_num_opcodes;
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