From b5bffab8d3454dd0a79eba112f387883cb041b51 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Sat, 2 Aug 2008 04:38:51 +0000 Subject: [PATCH] gas/ * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp". --- include/opcode/ChangeLog | 4 ++++ include/opcode/ppc.h | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 18aee1ff3..467cc5b60 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2008-08-01 Peter Bergner + + * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. + 2008-07-30 Michael J. Eager * ppc.h (PPC_OPCODE_405): Define. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a6b368ab0..0296b5967 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -157,6 +157,9 @@ extern const int powerpc_num_opcodes; /* Opcode is supported by PowerPC 405 processor. */ #define PPC_OPCODE_405 0x40000000 +/* Opcode is supported by Vector-Scalar (VSX) Unit */ +#define PPC_OPCODE_VSX 0x80000000 + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -312,6 +315,10 @@ extern const unsigned int num_powerpc_operands; #define PPC_OPERAND_FSL (0x20000) #define PPC_OPERAND_FCR (0x40000) #define PPC_OPERAND_UDI (0x80000) + +/* This operand names a vector-scalar unit register. The disassembler + prints these with a leading 'vs'. */ +#define PPC_OPERAND_VSR (0x100000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an