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arm: Fix the SP used in setting stack limit for standalone application. 

Move the instruction that saves SP before the mode check so that
applications that start in USER mode correctly set the stack limit.
This commit is contained in:
Srinath Parvathaneni 2023-03-03 12:45:40 +00:00 committed by Richard Earnshaw
parent 68db1fa7ba
commit b782dcb2b3
2 changed files with 2 additions and 4 deletions
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3
libgloss/arm/crt0.S
View File

@ -149,13 +149,12 @@
#if (__ARM_ARCH_PROFILE != 'M')
/* Following code is compatible for both ARM and Thumb ISA. */
mrs r4, CPSR
mov r3, sp /* Save input SP value. */
/* Test mode bits - in User of all are 0. */
tst r4, #(CPSR_M_MASK)
/* "eq" means r4 AND #0x0F is 0. */
beq .Lskip_cpu_modes
mov r3, sp /* Save input SP value. */
/* FIQ mode, interrupts disabled. */
mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
msr CPSR_c, r1

3
newlib/libc/sys/arm/crt0.S
View File

@ -149,13 +149,12 @@
#if (__ARM_ARCH_PROFILE != 'M')
/* Following code is compatible for both ARM and Thumb ISA. */
mrs r4, CPSR
mov r3, sp /* Save input SP value. */
/* Test mode bits - in User of all are 0. */
tst r4, #(CPSR_M_MASK)
/* "eq" means r4 AND #0x0F is 0. */
beq .Lskip_cpu_modes
mov r3, sp /* Save input SP value. */
/* FIQ mode, interrupts disabled. */
mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
msr CPSR_c, r1