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47 Commits

Author SHA1 Message Date
Jeff Law 85038a8a7f * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, 
and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
 1999-08-06 16:03:53 +00:00
Jeff Law 55c98dbaae * hppa.h: Document 64 bit condition completers. 1999-08-06 15:49:29 +00:00
Jeff Law 978c8e91e3 * hppa.h (pa_opcodes): Change condition args to use '?' prefix. 1999-08-05 22:58:08 +00:00
Alan Modra 0274eb115d Support for gcc to generate 16-bit i386 code. (.code16gcc) 1999-08-04 10:07:41 +00:00
Jeff Law 83849fdd14 * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". 
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
 1999-07-28 10:31:15 +00:00
Jeff Law 733df03348 * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, 
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
 1999-07-28 08:06:30 +00:00
Nick Clifton 34301951e0 Rename F_SOFTFLOAt to F_SOFT_FLOAT for compatability with include/elf/arm.h 1999-07-17 15:40:17 +00:00
Richard Henderson ae2271b23a Jakub Jelinek <jj@ultra.linux.cz> 
* sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions
        flag (as per SCD2.4.1).
 1999-07-16 21:36:38 +00:00
Richard Henderson 8647c02950 Jakub Jelinek <jj@ultra.linux.cz> 
* sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not
        ELF64_R_SYM bits.
 1999-07-16 21:26:39 +00:00
Nick Clifton 939a5db65a 1999-06-21 Philip Blundell <pb@nexus.co.uk> 
* arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define.
 1999-07-15 01:35:40 +00:00
Nick Clifton 2dbc8e9c1e 1999-06-21 Philip Blundell <pb@nexus.co.uk> 
* arm.h (F_SOFTFLOAT): Define.
 1999-07-15 01:34:30 +00:00
Alan Modra 02309525c5 8 
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
 1999-07-13 07:41:47 +00:00
Alan Modra bec8046d67 o 
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
 1999-07-13 07:41:46 +00:00
Andreas Schwab de58574b9b * m68k.h (EF_CPU32): Move definition inside multiple inclusion 
guard.
 1999-07-13 00:50:47 +00:00
Ian Lance Taylor 1e2fe5b32d * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is 
defined as 0.
 1999-07-12 11:12:37 +00:00
Ian Lance Taylor 19e94c3e01 * ansidecl.h: Copy attribute support macros from egcs. 1999-07-11 19:15:01 +00:00
Richard Henderson 192e3343c3 * sparc.h (ELF64_R_TYPE_DATA): Sign extend the value. 
(ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data.
        (DT_SPARC_PLTFMT): Delete.
 1999-07-08 16:01:06 +00:00
Nick Clifton bdc7824ee5 Define F_ARM_5 1999-07-05 07:29:04 +00:00
Jeff Law ca7cd5dc64 * hppa.h (struct pa_opcode): Add new field "flags". 
(FLAGS_STRICT): Define.
 1999-06-30 23:20:56 +00:00
Jeff Law 386449a2f8 * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. 1999-06-25 03:29:45 +00:00
Jeff Law 233881c2a2 * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. 1999-06-25 03:23:12 +00:00
Mark Mitchell 71bc641897 * bfdlink.h (struct bfd_link_hash_entry): Add init_function and 
fini_function.
 1999-06-23 11:03:45 +00:00
Alan Modra 30b962fd67 P 
include/opcode/i386.h: Allow bswapl, arplw, and other dodgy insns.
opcodes/i386-dis.c: Fix a comment
 1999-06-23 06:00:09 +00:00
Jeff Law 5f609326fb 8 
* hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type.
 1999-06-21 15:37:49 +00:00
Jeff Law dd8f7f0d2e b 
* hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type.
 1999-06-21 15:37:48 +00:00
Mark Mitchell 154acdedb7 * mips.h (Elf32_Internal_Msym): New structure. 
(Elf32_External_Msym): Likewise.
	(ELF32_MS_REL_INDEX): New macro.
	(ELF32_MS_FLAGS): Likewise.
	(ELF32_MS_INFO): Likewise.
 1999-06-21 06:57:35 +00:00
Nick Clifton 2e07d71fcd Add -M command line switch to objdump - text of switch is passed on to disassembler 
Add support for register name set selection ot ARM disassembler.
 1999-06-16 02:24:26 +00:00
Richard Henderson de7d321068 Jakub Jelinek <jj@ultra.linux.cz> 
* sparc.h (R_SPARC_max_std): Define.
 1999-06-10 21:00:53 +00:00
Jeff Law 20794137e9 � 
* hppa.h: Update with various changes from newest PA ELF
        specifications.
 1999-06-09 14:22:08 +00:00
Jeff Law 513edd10e1 . 
* hppa.h: Update with various changes from newest PA ELF
        specifications.
 1999-06-09 14:22:07 +00:00
Ian Lance Taylor a52fa432a8 * common.h (EM_PPC64): Define. 1999-06-03 08:20:07 +00:00
Richard Henderson e461c6c23c * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. 1999-06-03 03:26:17 +00:00
Richard Henderson 22bc31fc03 Stu Grossman <grossman@babylon-5.cygnus.com> 
* dwarf.h: Add LANG_JAVA.
        * dwarf2.h: Add DW_LANG_Java.
 1999-06-02 18:14:14 +00:00
Nick Clifton f17c053f8b Define ELFOSABI_ARM 1999-05-29 10:42:45 +00:00
Jeff Law 664151086b * hppa.h (pa_opcodes): Move integer arithmetic instructions after 
integer logical instructions.
 1999-05-28 14:26:52 +00:00
Nick Clifton 8d7a95a647 Update comment 1999-05-28 10:47:30 +00:00
Ian Lance Taylor 6a26bbce7b 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> 
* m68k.h: Document new formats `E', `G', `H' and new places `N',
	`n', `o'.
	* m68k.h: Define mcf5206e, mcf5307, mcf.  Document new format `u'
	and new places `m', `M', `h'.
 1999-05-27 22:31:03 +00:00
Ian Lance Taylor a4b15b89f4 * i960.h: New file. 1999-05-27 21:29:05 +00:00
Jeff Law 4b69b0a1f1 * hppa.h (pa_opcodes): Add several processor specific system 
instructions.
 1999-05-27 03:19:32 +00:00
Jeff Law 171cdecb9f * hppa.h (pa_opcodes): Add second entry for "comb", "comib", 
"addb", and "addib" to be used by the disassembler.
 1999-05-26 16:04:11 +00:00
Nick Clifton 4f70a0b8a9 Renumber cpu flag bits to avoid collision with PE flag bits 1999-05-19 07:25:59 +00:00
Nick Clifton 0ceedff1a6 Add PLT relolcs 1999-05-16 13:57:59 +00:00
Nick Clifton 04759263df Defined rva relocations. 1999-05-15 15:13:18 +00:00
Alan Modra 4b5775a3e9 P 
i386 PIII SIMD support, remove ReverseRegRegmem kludge
tidy a few things in i386 intel mode disassembly
 1999-05-13 06:00:27 +00:00
Richard Henderson a594afbb42 * ppc.h (PPC_OPCODE_64_BRIDGE): New. 1999-05-08 23:28:34 +00:00
Catherine Moore e2e59ff4eb * m68k.h (EF_CPU32): Define. 1999-05-05 10:57:16 +00:00
Richard Henderson a3acbf4694 19990502 sourceware import 1999-05-03 07:29:06 +00:00