306 lines
12 KiB
C
306 lines
12 KiB
C
/* pyramid.opcode.h -- gdb initial attempt.
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Copyright 2001 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* pyramid opcode table: wot to do with this
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particular opcode */
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struct pyr_datum
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{
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char nargs;
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char * args; /* how to compile said opcode */
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unsigned long mask; /* Bit vector: which operand modes are valid
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for this opcode */
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unsigned char code; /* op-code (always 6(?) bits */
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};
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typedef struct pyr_insn_format
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{
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unsigned int mode :4;
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unsigned int operator :8;
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unsigned int index_scale :2;
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unsigned int index_reg :6;
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unsigned int operand_1 :6;
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unsigned int operand_2:6;
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} pyr_insn_format;
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/* We store four bytes of opcode for all opcodes.
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Pyramid is sufficiently RISCy that:
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- insns are always an integral number of words;
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- the length of any insn can be told from the first word of
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the insn. (ie, if there are zero, one, or two words of
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immediate operand/offset).
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The args component is a string containing two characters for each
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operand of the instruction. The first specifies the kind of operand;
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the second, the place it is stored. */
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/* Kinds of operands:
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mask assembler syntax description
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0x0001: movw Rn,Rn register to register
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0x0002: movw K,Rn quick immediate to register
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0x0004: movw I,Rn long immediate to register
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0x0008: movw (Rn),Rn register indirect to register
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movw (Rn)[x],Rn register indirect to register
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0x0010: movw I(Rn),Rn offset register indirect to register
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movw I(Rn)[x],Rn offset register indirect, indexed, to register
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0x0020: movw Rn,(Rn) register to register indirect
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0x0040: movw K,(Rn) quick immediate to register indirect
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0x0080: movw I,(Rn) long immediate to register indirect
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0x0100: movw (Rn),(Rn) register indirect to-register indirect
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0x0100: movw (Rn),(Rn) register indirect to-register indirect
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0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
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0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
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0x0400: movw Rn,I(Rn) register to register indirect+offset
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0x0800: movw K,I(Rn) quick immediate to register indirect+offset
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0x1000: movw I,I(Rn) long immediate to register indirect+offset
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0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset
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0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect
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+offset
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0x0000: (irregular) ???
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Each insn has a four-bit field encoding the type(s) of its operands.
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*/
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/* Some common combinations
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*/
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/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
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#define GEN_TO_REG (31)
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#define UNKNOWN ((unsigned long)-1)
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#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
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#define CONVERT (1|8|0x10|0x20|0x200)
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#define K_TO_REG (2)
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#define I_TO_REG (4)
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#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
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#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
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/* The assembler requires that this array be sorted as follows:
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all instances of the same mnemonic must be consecutive.
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All instances of the same mnemonic with the same number of operands
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must be consecutive.
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*/
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struct pyr_opcode /* pyr opcode text */
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{
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char * name; /* opcode name: lowercase string [key] */
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struct pyr_datum datum; /* rest of opcode table [datum] */
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};
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#define pyr_how args
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#define pyr_nargs nargs
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#define pyr_mask mask
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#define pyr_name name
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struct pyr_opcode pyr_opcodes[] =
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{
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{"movb", { 2, "", UNKNOWN, 0x11}, },
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{"movh", { 2, "", UNKNOWN, 0x12} },
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{"movw", { 2, "", ANY, 0x10} },
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{"movl", { 2, "", ANY, 0x13} },
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{"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} },
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{"mnegf", { 2, "", 0x1, 0x15} },
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{"mnegd", { 2, "", 0x1, 0x16} },
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{"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} },
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{"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} },
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{"mabsf", { 2, "", 0x1, 0x19} },
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{"mabsd", { 2, "", 0x1, 0x1a} },
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{"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} },
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{"mtstf", { 2, "", 0x1, 0x1d} },
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{"mtstd", { 2, "", 0x1, 0x1e} },
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{"mova", { 2, "", 0x8|0x10, 0x1f} },
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{"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} },
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{"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} },
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/* 2 insns out of order here */
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{"movbl", { 2, "", 1, 0x4f} },
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{"filbl", { 2, "", 1, 0x4e} },
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{"cvtbw", { 2, "", CONVERT, 0x22} },
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{"cvthw", { 2, "", CONVERT, 0x23} },
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{"cvtwb", { 2, "", CONVERT, 0x24} },
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{"cvtwh", { 2, "", CONVERT, 0x25} },
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{"cvtwf", { 2, "", CONVERT, 0x26} },
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{"cvtwd", { 2, "", CONVERT, 0x27} },
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{"cvtfw", { 2, "", CONVERT, 0x28} },
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{"cvtfd", { 2, "", CONVERT, 0x29} },
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{"cvtdw", { 2, "", CONVERT, 0x2a} },
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{"cvtdf", { 2, "", CONVERT, 0x2b} },
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{"addw", { 2, "", GEN_TO_REG, 0x40} },
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{"addwc", { 2, "", GEN_TO_REG, 0x41} },
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{"subw", { 2, "", GEN_TO_REG, 0x42} },
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{"subwb", { 2, "", GEN_TO_REG, 0x43} },
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{"rsubw", { 2, "", GEN_TO_REG, 0x44} },
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{"mulw", { 2, "", GEN_TO_REG, 0x45} },
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{"emul", { 2, "", GEN_TO_REG, 0x47} },
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{"umulw", { 2, "", GEN_TO_REG, 0x46} },
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{"divw", { 2, "", GEN_TO_REG, 0x48} },
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{"ediv", { 2, "", GEN_TO_REG, 0x4a} },
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{"rdivw", { 2, "", GEN_TO_REG, 0x4b} },
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{"udivw", { 2, "", GEN_TO_REG, 0x49} },
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{"modw", { 2, "", GEN_TO_REG, 0x4c} },
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{"umodw", { 2, "", GEN_TO_REG, 0x4d} },
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{"addf", { 2, "", 1, 0x50} },
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{"addd", { 2, "", 1, 0x51} },
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{"subf", { 2, "", 1, 0x52} },
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{"subd", { 2, "", 1, 0x53} },
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{"mulf", { 2, "", 1, 0x56} },
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{"muld", { 2, "", 1, 0x57} },
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{"divf", { 2, "", 1, 0x58} },
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{"divd", { 2, "", 1, 0x59} },
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{"cmpb", { 2, "", UNKNOWN, 0x61} },
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{"cmph", { 2, "", UNKNOWN, 0x62} },
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{"cmpw", { 2, "", UNKNOWN, 0x60} },
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{"ucmpb", { 2, "", UNKNOWN, 0x66} },
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/* WHY no "ucmph"??? */
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{"ucmpw", { 2, "", UNKNOWN, 0x65} },
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{"xchw", { 2, "", UNKNOWN, 0x0f} },
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{"andw", { 2, "", GEN_TO_REG, 0x30} },
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{"orw", { 2, "", GEN_TO_REG, 0x31} },
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{"xorw", { 2, "", GEN_TO_REG, 0x32} },
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{"bicw", { 2, "", GEN_TO_REG, 0x33} },
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{"lshlw", { 2, "", GEN_TO_REG, 0x38} },
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{"ashlw", { 2, "", GEN_TO_REG, 0x3a} },
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{"ashll", { 2, "", GEN_TO_REG, 0x3c} },
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{"ashrw", { 2, "", GEN_TO_REG, 0x3b} },
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{"ashrl", { 2, "", GEN_TO_REG, 0x3d} },
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{"rotlw", { 2, "", GEN_TO_REG, 0x3e} },
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{"rotrw", { 2, "", GEN_TO_REG, 0x3f} },
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/* push and pop insns are "going away next release". */
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{"pushw", { 2, "", GEN_TO_REG, 0x0c} },
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{"popw", { 2, "", (0x1|0x8|0x10), 0x0d} },
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{"pusha", { 2, "", (0x8|0x10), 0x0e} },
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{"bitsw", { 2, "", UNKNOWN, 0x35} },
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{"bitcw", { 2, "", UNKNOWN, 0x36} },
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/* some kind of ibra/dbra insns??*/
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{"icmpw", { 2, "", UNKNOWN, 0x67} },
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{"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/
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{"acmpw", { 2, "", 1, 0x6b} },
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/* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
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insn with a 2nd op of tr14. The assembler will have to grok this. */
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{"call", { 2, "", GEN_TO_REG, 0x04} },
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{"call", { 1, "", GEN_TO_REG, 0x04} },
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{"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/
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/* Ret is usually written as a 0-op insn, but gets disassembled as a
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1-op insn. The operand is always tr15. */
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{"ret", { 0, "", UNKNOWN, 0x09} },
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{"ret", { 1, "", UNKNOWN, 0x09} },
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{"adsf", { 2, "", (1|2|4), 0x08} },
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{"retd", { 2, "", UNKNOWN, 0x0a} },
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{"btc", { 2, "", UNKNOWN, 0x01} },
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{"bfc", { 2, "", UNKNOWN, 0x02} },
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/* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
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{"jump", { 1, "", UNKNOWN, 0x00} },
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{"btp", { 2, "", UNKNOWN, 0xf00} },
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/* read control-stack pointer is another 1-or-2 operand insn. */
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{"rcsp", { 2, "", UNKNOWN, 0x01f} },
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{"rcsp", { 1, "", UNKNOWN, 0x01f} }
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};
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/* end: pyramid.opcode.h */
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/* One day I will have to take the time to find out what operands
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are valid for these insns, and guess at what they mean.
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I can't imagine what the "I???" insns (iglob, etc) do.
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the arithmetic-sounding insns ending in "p" sound awfully like BCD
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arithmetic insns:
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dshlp -> Decimal SHift Left Packed
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dshrp -> Decimal SHift Right Packed
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and cvtlp would be convert long to packed.
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I have no idea how the operands are interpreted; but having them be
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a long register with (address, length) of an in-memory packed BCD operand
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would not be surprising.
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They are unlikely to be a packed bcd string: 64 bits of long give
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is only 15 digits+sign, which isn't enough for COBOL.
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*/
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#if 0
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{"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/
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/* The OSx Operating System Porting Guide claims SSL does things
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with tr12 (a register reserved to it) to do with static block-structure
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references. SSL=Set Static Link? It's "Going away next release". */
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{"ssl", { 2, "", UNKNOWN, 0x00} },
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{"ccmps", { 2, "", UNKNOWN, 0x00} },
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{"lcd", { 2, "", UNKNOWN, 0x00} },
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{"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/
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{"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/
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{"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/
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{"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/
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{"ldti", { 2, "", UNKNOWN, 0x00} },
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{"ldb", { 2, "", UNKNOWN, 0x00} },
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{"stp", { 2, "", UNKNOWN, 0x00} },
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{"stti", { 2, "", UNKNOWN, 0x00} },
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{"stb", { 2, "", UNKNOWN, 0x00} },
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{"stu", { 2, "", UNKNOWN, 0x00} },
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{"addp", { 2, "", UNKNOWN, 0x00} },
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{"subp", { 2, "", UNKNOWN, 0x00} },
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{"mulp", { 2, "", UNKNOWN, 0x00} },
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{"divp", { 2, "", UNKNOWN, 0x00} },
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{"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */
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{"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */
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{"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/
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{"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/
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{"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/
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{"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/
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{"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/
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{"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/
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{"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/
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{"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/
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{"cmovs", { 2, "", UNKNOWN, 0x00} },
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{"rsubw", { 2, "", UNKNOWN, 0x00} },
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{"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */
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{"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */
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{"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */
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{"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/
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{"callr", { 2, "", UNKNOWN, 0x00} },
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{"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/
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{"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/
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{"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/
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{"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/
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{"ssi", { 2, "", UNKNOWN, 0x00} },
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{"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/
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{"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */
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{"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/
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{"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/
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{"flic", { 2, "", UNKNOWN, 0x00} },
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{"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */
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{"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */
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{"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */
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{"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */
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{"lamst", { 2, "", UNKNOWN, 0x00} },
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{"tio", { 2, "", UNKNOWN, 0x00} },
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#endif
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