121 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
			
		
		
	
	
			121 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
| /* The interrupt table.
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|  *
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|  * Copyright (c) 2006 CodeSourcery Inc
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|  *
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|  * The authors hereby grant permission to use, copy, modify, distribute,
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|  * and license this software and its documentation for any purpose, provided
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|  * that existing copyright notices are retained in all copies and that this
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|  * notice is included verbatim in any distributions. No written agreement,
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|  * license, or royalty fee is required for any of the authorized uses.
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|  * Modifications to this software may be copyrighted by their authors
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|  * and need not follow the licensing terms described here, provided that
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|  * the new terms are clearly indicated on the first page of each file where
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|  * they apply.
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|  */
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| 
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| 	.macro SLOT,n,prefix=,suffix=
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| 	.long __\prefix\n\suffix
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| 	.endm
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| 
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| 	.macro ISR n
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| 	SLOT \n,interrupt,
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| 	.endm
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| 
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| 	.macro TRAP n
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| 	SLOT \n,trap,
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| 	.endm
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| 
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| 	.macro FP n
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| 	SLOT \n,fp_,
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| 	.endm
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| 
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| 	.macro UNIMP_OPCODE n
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| 	SLOT \n,unimplemented_,_opcode
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| 	.endm
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| 
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| 	.macro BREAKPOINT_DEBUG n
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| 	SLOT \n,,_breakpoint_debug_interrupt
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| 	.endm
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| 
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| 	.section .interrupt_vector,"a"
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| 
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| 	.globl __interrupt_vector
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| __interrupt_vector:
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| 	
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| 	.long __stack 				/* 0 */
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| 	.long __reset				/* 1 */
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| 	.long __access_error			/* 2 */
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| 	.long __address_error			/* 3 */
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| 	.long __illegal_instruction		/* 4 */
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| 	.long __divide_by_zero			/* 5 */
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| 	ISR 6
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| 	ISR 7
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| 	.long __privilege_violation		/* 8 */
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| 	.long __trace				/* 9 */
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| 	UNIMP_OPCODE line_a			/* 10 */
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| 	UNIMP_OPCODE line_f			/* 11 */
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| 	BREAKPOINT_DEBUG non_pc			/* 12 */
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| 	BREAKPOINT_DEBUG pc			/* 13 */
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| 	.long __format_error			/* 14 */
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| 	.irp N,15,16,17,18,19,20,21,22,23
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| 	ISR \N					/* [15,24) */
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| 	.endr
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| 	.long __spurious_interrupt		/* 24 */
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| 	.irp N,25,26,27,28,29,30,31
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| 	ISR \N					/* [25,32) */
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| 	.endr
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| 	.irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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| 	TRAP \N					/* [32,48) */
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| 	.endr
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| 	FP branch_unordered			/* 48 */
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| 	FP inexact_result			/* 49 */
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| 	FP divide_by_zero			/* 50 */
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| 	FP underflow				/* 51 */
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| 	FP operand_error			/* 52 */
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| 	FP overflow				/* 53 */
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| 	FP input_not_a_number			/* 54 */
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| 	FP input_denormalized_number		/* 55 */
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| 	.irp N,56,57,58,59,60
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| 	ISR \N					/* [56,61) */
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| 	.endr
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| 	.long __unsupported_instruction		/* 61 */
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| 	.irp N,62,63
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| 	ISR \N					/* [62,64) */
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| 	.endr
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| 	.irp N,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
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| 	ISR \N			/* [64,80) */
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| 	.endr
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| 	.irp N,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
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| 	ISR \N			/* [80,96) */
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| 	.endr
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| 	.irp N,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111
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| 	ISR \N			/* [96,112) */
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| 	.endr
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| 	.irp N,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
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| 	ISR \N			/* [112,128) */
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| 	.endr
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| 	.irp N,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143
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| 	ISR \N			/* [128,144) */
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| 	.endr
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| 	.irp N,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159
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| 	ISR \N			/* [144,160) */
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| 	.endr
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| 	.irp N,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175
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| 	ISR \N			/* [160,176) */
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| 	.endr
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| 	.irp N,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191
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| 	ISR \N			/* [176,192) */
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| 	.endr
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| 	.irp N,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207
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| 	ISR \N			/* [192,208) */
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| 	.endr
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| 	.irp N,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223
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| 	ISR \N			/* [208,224) */
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| 	.endr
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| 	.irp N,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239
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| 	ISR \N			/* [224,240) */
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| 	.endr
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| 	.irp N,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255
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| 	ISR \N			/* [240,256) */
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| 	.endr
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