393 lines
14 KiB
C
393 lines
14 KiB
C
/* ia64.h -- Header file for ia64 opcode table
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Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
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#ifndef opcode_ia64_h
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#define opcode_ia64_h
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#include <sys/types.h>
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#include "bfd.h"
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typedef BFD_HOST_U_64_BIT ia64_insn;
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enum ia64_insn_type
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{
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IA64_TYPE_NIL = 0, /* illegal type */
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IA64_TYPE_A, /* integer alu (I- or M-unit) */
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IA64_TYPE_I, /* non-alu integer (I-unit) */
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IA64_TYPE_M, /* memory (M-unit) */
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IA64_TYPE_B, /* branch (B-unit) */
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IA64_TYPE_F, /* floating-point (F-unit) */
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IA64_TYPE_X, /* long encoding (X-unit) */
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IA64_TYPE_DYN, /* Dynamic opcode */
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IA64_NUM_TYPES
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};
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enum ia64_unit
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{
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IA64_UNIT_NIL = 0, /* illegal unit */
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IA64_UNIT_I, /* integer unit */
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IA64_UNIT_M, /* memory unit */
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IA64_UNIT_B, /* branching unit */
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IA64_UNIT_F, /* floating-point unit */
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IA64_UNIT_L, /* long "unit" */
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IA64_UNIT_X, /* may be integer or branch unit */
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IA64_NUM_UNITS
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};
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/* Changes to this enumeration must be propagated to the operand table in
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bfd/cpu-ia64-opc.c
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*/
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enum ia64_opnd
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{
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IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
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/* constants */
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IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
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IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
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IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
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IA64_OPND_C1, /* the constant 1 */
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IA64_OPND_C8, /* the constant 8 */
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IA64_OPND_C16, /* the constant 16 */
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IA64_OPND_GR0, /* gr0 */
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IA64_OPND_IP, /* instruction pointer (ip) */
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IA64_OPND_PR, /* predicate register (pr) */
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IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
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IA64_OPND_PSR, /* processor status register (psr) */
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IA64_OPND_PSR_L, /* processor status register L (psr.l) */
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IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
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/* register operands: */
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IA64_OPND_AR3, /* third application register # (bits 20-26) */
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IA64_OPND_B1, /* branch register # (bits 6-8) */
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IA64_OPND_B2, /* branch register # (bits 13-15) */
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IA64_OPND_CR3, /* third control register # (bits 20-26) */
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IA64_OPND_F1, /* first floating-point register # */
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IA64_OPND_F2, /* second floating-point register # */
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IA64_OPND_F3, /* third floating-point register # */
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IA64_OPND_F4, /* fourth floating-point register # */
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IA64_OPND_P1, /* first predicate # */
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IA64_OPND_P2, /* second predicate # */
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IA64_OPND_R1, /* first register # */
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IA64_OPND_R2, /* second register # */
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IA64_OPND_R3, /* third register # */
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IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
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/* indirect operands: */
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IA64_OPND_CPUID_R3, /* cpuid[reg] */
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IA64_OPND_DBR_R3, /* dbr[reg] */
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IA64_OPND_DTR_R3, /* dtr[reg] */
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IA64_OPND_ITR_R3, /* itr[reg] */
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IA64_OPND_IBR_R3, /* ibr[reg] */
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IA64_OPND_MR3, /* memory at addr of third register # */
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IA64_OPND_MSR_R3, /* msr[reg] */
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IA64_OPND_PKR_R3, /* pkr[reg] */
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IA64_OPND_PMC_R3, /* pmc[reg] */
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IA64_OPND_PMD_R3, /* pmd[reg] */
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IA64_OPND_RR_R3, /* rr[reg] */
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/* immediate operands: */
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IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
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IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
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IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
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IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
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IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
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IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
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IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
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IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
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IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
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IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
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IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
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IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
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IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
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IA64_OPND_SOF, /* 8-bit stack frame size */
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IA64_OPND_SOL, /* 8-bit size of locals */
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IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
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IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
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IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
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IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
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IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
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IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
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IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
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IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
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IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
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IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
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IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
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IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
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IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
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IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
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IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
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IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
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IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
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IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
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IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
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IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
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IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
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IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
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IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
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IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
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IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
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IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
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IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
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IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
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IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
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IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */
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IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
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};
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enum ia64_dependency_mode
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{
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IA64_DV_RAW,
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IA64_DV_WAW,
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IA64_DV_WAR,
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};
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enum ia64_dependency_semantics
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{
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IA64_DVS_NONE,
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IA64_DVS_IMPLIED,
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IA64_DVS_IMPLIEDF,
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IA64_DVS_DATA,
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IA64_DVS_INSTR,
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IA64_DVS_SPECIFIC,
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IA64_DVS_STOP,
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IA64_DVS_OTHER,
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};
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enum ia64_resource_specifier
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{
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IA64_RS_ANY,
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IA64_RS_AR_K,
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IA64_RS_AR_UNAT,
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IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
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IA64_RS_ARb, /* 48-63, 112-127 */
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IA64_RS_BR,
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IA64_RS_CFM,
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IA64_RS_CPUID,
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IA64_RS_CR_IRR,
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IA64_RS_CR_LRR,
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IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
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IA64_RS_DBR,
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IA64_RS_FR,
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IA64_RS_FRb,
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IA64_RS_GR0,
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IA64_RS_GR,
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IA64_RS_IBR,
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IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
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IA64_RS_MSR,
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IA64_RS_PKR,
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IA64_RS_PMC,
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IA64_RS_PMD,
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IA64_RS_PR, /* non-rotating, 1-15 */
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IA64_RS_PRr, /* rotating, 16-62 */
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IA64_RS_PR63,
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IA64_RS_RR,
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IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
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IA64_RS_CRX, /* CRs not in RS_CR */
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IA64_RS_PSR, /* PSR bits */
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IA64_RS_RSE, /* implementation-specific RSE resources */
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IA64_RS_AR_FPSR,
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};
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enum ia64_rse_resource
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{
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IA64_RSE_N_STACKED_PHYS,
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IA64_RSE_BOF,
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IA64_RSE_STORE_REG,
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IA64_RSE_LOAD_REG,
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IA64_RSE_BSPLOAD,
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IA64_RSE_RNATBITINDEX,
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IA64_RSE_CFLE,
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IA64_RSE_NDIRTY,
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};
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/* Information about a given resource dependency */
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struct ia64_dependency
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{
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/* Name of the resource */
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const char *name;
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/* Does this dependency need further specification? */
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enum ia64_resource_specifier specifier;
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/* Mode of dependency */
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enum ia64_dependency_mode mode;
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/* Dependency semantics */
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enum ia64_dependency_semantics semantics;
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/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
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#define REG_NONE (-1)
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int regindex;
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/* Special info on semantics */
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const char *info;
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};
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/* Two arrays of indexes into the ia64_dependency table.
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chks are dependencies to check for conflicts when an opcode is
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encountered; regs are dependencies to register (mark as used) when an
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opcode is used. chks correspond to readers (RAW) or writers (WAW or
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WAR) of a resource, while regs correspond to writers (RAW or WAW) and
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readers (WAR) of a resource. */
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struct ia64_opcode_dependency
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{
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int nchks;
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const unsigned short *chks;
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int nregs;
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const unsigned short *regs;
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};
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/* encode/extract the note/index for a dependency */
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#define RDEP(N,X) (((N)<<11)|(X))
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#define NOTE(X) (((X)>>11)&0x1F)
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#define DEP(X) ((X)&0x7FF)
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/* A template descriptor describes the execution units that are active
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for each of the three slots. It also specifies the location of
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instruction group boundaries that may be present between two slots. */
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struct ia64_templ_desc
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{
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int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
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enum ia64_unit exec_unit[3];
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const char *name;
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};
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/* The opcode table is an array of struct ia64_opcode. */
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struct ia64_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The type of the instruction: */
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enum ia64_insn_type type;
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/* Number of output operands: */
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int num_outputs;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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ia64_insn opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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ia64_insn mask;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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enum ia64_opnd operands[5];
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/* One bit flags for the opcode. These are primarily used to
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indicate specific processors and environments support the
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instructions. The defined values are listed below. */
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unsigned int flags;
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/* Used by ia64_find_next_opcode (). */
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short ent_index;
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/* Opcode dependencies. */
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const struct ia64_opcode_dependency *dependencies;
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};
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/* Values defined for the flags field of a struct ia64_opcode. */
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#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
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#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
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#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
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#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
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#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
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#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
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#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
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#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
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#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
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#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
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#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
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/* A macro to extract the major opcode from an instruction. */
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#define IA64_OP(i) (((i) >> 37) & 0xf)
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enum ia64_operand_class
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{
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IA64_OPND_CLASS_CST, /* constant */
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IA64_OPND_CLASS_REG, /* register */
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IA64_OPND_CLASS_IND, /* indirect register */
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IA64_OPND_CLASS_ABS, /* absolute value */
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IA64_OPND_CLASS_REL, /* IP-relative value */
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};
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/* The operands table is an array of struct ia64_operand. */
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struct ia64_operand
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{
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enum ia64_operand_class class;
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/* Set VALUE as the operand bits for the operand of type SELF in the
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instruction pointed to by CODE. If an error occurs, *CODE is not
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modified and the returned string describes the cause of the
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error. If no error occurs, NULL is returned. */
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const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code);
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/* Extract the operand bits for an operand of type SELF from
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instruction CODE store them in *VALUE. If an error occurs, the
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cause of the error is described by the string returned. If no
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error occurs, NULL is returned. */
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const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
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ia64_insn *value);
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/* A string whose meaning depends on the operand class. */
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const char *str;
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struct bit_field
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{
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/* The number of bits in the operand. */
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int bits;
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/* How far the operand is left shifted in the instruction. */
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int shift;
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}
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field[4]; /* no operand has more than this many bit-fields */
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unsigned int flags;
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const char *desc; /* brief description */
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};
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/* Values defined for the flags field of a struct ia64_operand. */
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/* Disassemble as signed decimal (instead of hex): */
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#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
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/* Disassemble as unsigned decimal (instead of hex): */
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#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
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extern const struct ia64_templ_desc ia64_templ_desc[16];
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/* The tables are sorted by major opcode number and are otherwise in
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the order in which the disassembler should consider instructions. */
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extern struct ia64_opcode ia64_opcodes_a[];
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extern struct ia64_opcode ia64_opcodes_i[];
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extern struct ia64_opcode ia64_opcodes_m[];
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extern struct ia64_opcode ia64_opcodes_b[];
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extern struct ia64_opcode ia64_opcodes_f[];
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extern struct ia64_opcode ia64_opcodes_d[];
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extern struct ia64_opcode *ia64_find_opcode (const char *name);
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extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
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extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
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enum ia64_insn_type type);
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extern void ia64_free_opcode (struct ia64_opcode *ent);
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extern const struct ia64_dependency *ia64_find_dependency (int index);
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/* To avoid circular library dependencies, this array is implemented
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in bfd/cpu-ia64-opc.c: */
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extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
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#endif /* opcode_ia64_h */
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