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acadia-newlib/newlib/libm/machine/riscv
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Mike Frysinger a100e80fc9 require autoconf-2.69 exactly 
The newlib & libgloss dirs are already generated using autoconf-2.69.
To avoid merging new code and/or accidental regeneration using diff
versions, leverage config/override.m4 to pin to 2.69 exactly.  This
matches what gcc/binutils/gdb are already doing.

The README file already says to use autoconf-2.69.

To accomplish this, it's just as simple as adding -I flags to the
top-level config/ dir when running aclocal.  This is because the
override.m4 file overrides AC_INIT to first require the specific
autoconf version before calling the real AC_INIT.
 		2022-01-14 15:24:33 -05:00
..
Makefile.am require autoconf-2.69 exactly 2022-01-14 15:24:33 -05:00
Makefile.in require autoconf-2.69 exactly 2022-01-14 15:24:33 -05:00
aclocal.m4 require autoconf-2.69 exactly 2022-01-14 15:24:33 -05:00
configure require autoconf-2.69 exactly 2022-01-14 15:24:33 -05:00
configure.ac require autoconf-2.69 exactly 2022-01-14 15:24:33 -05:00
e_sqrt.c libm/riscv: Fix machine-specific sqrt build process 2020-09-04 15:11:31 +02:00
ef_sqrt.c libm/riscv: Fix machine-specific sqrt build process 2020-09-04 15:11:31 +02:00
fe_dfl_env.c
…
feclearexcept.c
…
fegetenv.c
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fegetexceptflag.c
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fegetround.c
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feholdexcept.c
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feraiseexcept.c
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fesetenv.c
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fesetexceptflag.c
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fesetround.c
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fetestexcept.c
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feupdateenv.c
…
riscv_math.h RISC-V: Implment finite and fpclassify 2020-10-27 08:56:30 +01:00
s_copysign.c RISC-V: Add machine-specific implementation for isnan[f] and copysign[f] 2020-11-18 09:35:28 +01:00
s_fabs.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
s_finite.c RISC-V: NaN should return 0 for finite[f] 2020-10-29 09:39:35 +01:00
s_fma.c libm/riscv: Use common fma code when necessary 2020-09-04 15:11:31 +02:00
s_fmax.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
s_fmin.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
s_fpclassify.c RISC-V: Implment finite and fpclassify 2020-10-27 08:56:30 +01:00
s_isinf.c RISC-V: Fix wrong including file in s_isinf.c 2020-10-29 09:39:35 +01:00
s_isnan.c RISC-V: Add machine-specific implementation for isnan[f] and copysign[f] 2020-11-18 09:35:28 +01:00
s_llrint.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
s_llround.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
s_lrint.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
s_lround.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
sf_copysign.c RISC-V: Add machine-specific implementation for isnan[f] and copysign[f] 2020-11-18 09:35:28 +01:00
sf_fabs.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
sf_finite.c RISC-V: NaN should return 0 for finite[f] 2020-10-29 09:39:35 +01:00
sf_fma.c libm/riscv: Use common fma code when necessary 2020-09-04 15:11:31 +02:00
sf_fmax.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
sf_fmin.c RISC-V: Add fabs[f], fmax[f] and fmin[f]. 2020-10-27 08:56:30 +01:00
sf_fpclassify.c RISC-V: Implment finite and fpclassify 2020-10-27 08:56:30 +01:00
sf_isinf.c RISC-V: Implment finite and fpclassify 2020-10-27 08:56:30 +01:00
sf_isnan.c RISC-V: Add machine-specific implementation for isnan[f] and copysign[f] 2020-11-18 09:35:28 +01:00
sf_llrint.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
sf_llround.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
sf_lrint.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00
sf_lround.c RISC-V: Add machine-specific implementation for lrint[f], lround[f], llrint[f] and llround[f]. 2020-11-18 09:35:28 +01:00