372 lines
10 KiB
ArmAsm
372 lines
10 KiB
ArmAsm
/* This is a simple version of setjmp and longjmp for the PowerPC.
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Ian Lance Taylor, Cygnus Support, 9 Feb 1994.
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Modified by Jeff Johnston, Red Hat Inc. 2 Oct 2001.
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Modified by Sebastian Huber, embedded brains GmbH. 22 Sep 2022. */
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#include "ppc-asm.h"
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FUNC_START(setjmp)
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#ifdef __ALTIVEC__
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addi 3,3,15 # align Altivec to 16 byte boundary
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rlwinm 3,3,0,0,27
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#else
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addi 3,3,7 # align to 8 byte boundary
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rlwinm 3,3,0,0,28
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#endif
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#if __SPE__
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/* If we are E500, then save 64-bit registers. */
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evstdd 1,0(3) # offset 0
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evstdd 2,8(3) # offset 8
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evstdd 13,16(3) # offset 16
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evstdd 14,24(3) # offset 24
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evstdd 15,32(3) # offset 32
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evstdd 16,40(3) # offset 40
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evstdd 17,48(3) # offset 48
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evstdd 18,56(3) # offset 56
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evstdd 19,64(3) # offset 64
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evstdd 20,72(3) # offset 72
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evstdd 21,80(3) # offset 80
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evstdd 22,88(3) # offset 88
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evstdd 23,96(3) # offset 96
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evstdd 24,104(3) # offset 104
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evstdd 25,112(3) # offset 112
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evstdd 26,120(3) # offset 120
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evstdd 27,128(3) # offset 128
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evstdd 28,136(3) # offset 136
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evstdd 29,144(3) # offset 144
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evstdd 30,152(3) # offset 152
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evstdd 31,160(3) # offset 160
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/* Add 164 to r3 to account for the amount of data we just
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stored. Note that we are not adding 168 because the next
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store instruction uses an offset of 4. */
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addi 3,3,164
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#elif __powerpc64__
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/* In the first store, add 8 to r3 so that the subsequent floating
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point stores are aligned on an 8 byte boundary and the Altivec
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stores are aligned on a 16 byte boundary. */
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stdu 1,8(3) # offset 8
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stdu 2,8(3) # offset 16
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stdu 13,8(3) # offset 24
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stdu 14,8(3) # offset 32
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stdu 15,8(3) # offset 40
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stdu 16,8(3) # offset 48
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stdu 17,8(3) # offset 56
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stdu 18,8(3) # offset 64
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stdu 19,8(3) # offset 72
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stdu 20,8(3) # offset 80
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stdu 21,8(3) # offset 88
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stdu 22,8(3) # offset 96
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stdu 23,8(3) # offset 104
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stdu 24,8(3) # offset 112
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stdu 25,8(3) # offset 120
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stdu 26,8(3) # offset 128
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stdu 27,8(3) # offset 136
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stdu 28,8(3) # offset 144
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stdu 29,8(3) # offset 152
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stdu 30,8(3) # offset 160
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stdu 31,8(3) # offset 168
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mflr 4
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stdu 4,8(3) # offset 176
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mfcr 4
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stwu 4,8(3) # offset 184
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#else
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stw 1,0(3) # offset 0
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stwu 2,4(3) # offset 4
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stwu 13,4(3) # offset 8
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stwu 14,4(3) # offset 12
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stwu 15,4(3) # offset 16
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stwu 16,4(3) # offset 20
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stwu 17,4(3) # offset 24
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stwu 18,4(3) # offset 28
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stwu 19,4(3) # offset 32
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stwu 20,4(3) # offset 36
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stwu 21,4(3) # offset 40
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stwu 22,4(3) # offset 44
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stwu 23,4(3) # offset 48
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stwu 24,4(3) # offset 52
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stwu 25,4(3) # offset 56
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stwu 26,4(3) # offset 60
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stwu 27,4(3) # offset 64
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stwu 28,4(3) # offset 68
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stwu 29,4(3) # offset 72
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stwu 30,4(3) # offset 76
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stwu 31,4(3) # offset 80
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#endif
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#if !__powerpc64__
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/* If __SPE__, then add 84 to the offset shown from this point on until
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the end of this function. This difference comes from the fact that
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we save 21 64-bit registers instead of 21 32-bit registers above. */
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mflr 4
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stwu 4,4(3) # offset 84
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mfcr 4
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stwu 4,4(3) # offset 88
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# one word pad to get floating point aligned on 8 byte boundary
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#endif
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/* Check whether we need to save FPRs. Checking __NO_FPRS__
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on its own would be enough for GCC 4.1 and above, but older
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compilers only define _SOFT_FLOAT, so check both. */
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#if !defined (__NO_FPRS__) && !defined (_SOFT_FLOAT)
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#if defined (__rtems__) && !defined (__PPC_CPU_E6500__)
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/* For some RTEMS multilibs, the FPU and Altivec units are disabled
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during interrupt handling. Do not save and restore the
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corresponding registers in this case. */
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mfmsr 5
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andi. 5,5,0x2000
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beq 1f
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#endif
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/* If __powerpc64__, then add 96 to the offset shown from this point on until
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the end of this function. This difference comes from the fact that
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we save 23 64-bit registers instead of 23 32-bit registers above and
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we take alignement requirements of floating point and Altivec stores
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into account. */
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stfdu 14,8(3) # offset 96
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stfdu 15,8(3) # offset 104
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stfdu 16,8(3) # offset 112
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stfdu 17,8(3) # offset 120
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stfdu 18,8(3) # offset 128
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stfdu 19,8(3) # offset 136
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stfdu 20,8(3) # offset 144
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stfdu 21,8(3) # offset 152
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stfdu 22,8(3) # offset 160
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stfdu 23,8(3) # offset 168
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stfdu 24,8(3) # offset 176
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stfdu 25,8(3) # offset 184
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stfdu 26,8(3) # offset 192
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stfdu 27,8(3) # offset 200
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stfdu 28,8(3) # offset 208
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stfdu 29,8(3) # offset 216
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stfdu 30,8(3) # offset 224
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stfdu 31,8(3) # offset 232
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1:
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#endif
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/* This requires a total of 21 * 4 + 18 * 8 + 4 + 4 + 4
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bytes == 60 * 4 bytes == 240 bytes. */
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#ifdef __ALTIVEC__
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#if defined (__rtems__) && !defined (__PPC_CPU_E6500__)
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mfmsr 5
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andis. 5,5,0x200
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beq 1f
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#endif
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/* save Altivec vrsave and vr20-vr31 registers */
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mfspr 4,256 # vrsave register
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stwu 4,16(3) # offset 248
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addi 3,3,8
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stvx 20,0,3 # offset 256
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addi 3,3,16
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stvx 21,0,3 # offset 272
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addi 3,3,16
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stvx 22,0,3 # offset 288
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addi 3,3,16
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stvx 23,0,3 # offset 304
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addi 3,3,16
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stvx 24,0,3 # offset 320
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addi 3,3,16
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stvx 25,0,3 # offset 336
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addi 3,3,16
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stvx 26,0,3 # offset 352
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addi 3,3,16
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stvx 27,0,3 # offset 368
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addi 3,3,16
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stvx 28,0,3 # offset 384
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addi 3,3,16
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stvx 29,0,3 # offset 400
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addi 3,3,16
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stvx 30,0,3 # offset 416
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addi 3,3,16
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stvx 31,0,3 # offset 432
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1:
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/* This requires a total of 240 + 8 + 8 + 12 * 16 == 448 bytes. */
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#endif
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li 3,0
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blr
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FUNC_END(setjmp)
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FUNC_START(longjmp)
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#ifdef __ALTIVEC__
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addi 3,3,15 # align Altivec to 16 byte boundary
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rlwinm 3,3,0,0,27
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#else
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addi 3,3,7 # align to 8 byte boundary
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rlwinm 3,3,0,0,28
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#endif
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#if __SPE__
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/* If we are E500, then restore 64-bit registers. */
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evldd 1,0(3) # offset 0
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evldd 2,8(3) # offset 8
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evldd 13,16(3) # offset 16
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evldd 14,24(3) # offset 24
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evldd 15,32(3) # offset 32
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evldd 16,40(3) # offset 40
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evldd 17,48(3) # offset 48
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evldd 18,56(3) # offset 56
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evldd 19,64(3) # offset 64
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evldd 20,72(3) # offset 72
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evldd 21,80(3) # offset 80
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evldd 22,88(3) # offset 88
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evldd 23,96(3) # offset 96
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evldd 24,104(3) # offset 104
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evldd 25,112(3) # offset 112
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evldd 26,120(3) # offset 120
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evldd 27,128(3) # offset 128
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evldd 28,136(3) # offset 136
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evldd 29,144(3) # offset 144
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evldd 30,152(3) # offset 152
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evldd 31,160(3) # offset 160
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/* Add 164 to r3 to account for the amount of data we just
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loaded. Note that we are not adding 168 because the next
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load instruction uses an offset of 4. */
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addi 3,3,164
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#elif __powerpc64__
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/* In the first load, add 8 to r3 so that the subsequent floating
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point loades are aligned on an 8 byte boundary and the Altivec
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loads are aligned on a 16 byte boundary. */
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ldu 1,8(3) # offset 8
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ldu 2,8(3) # offset 16
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ldu 13,8(3) # offset 24
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ldu 14,8(3) # offset 32
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ldu 15,8(3) # offset 40
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ldu 16,8(3) # offset 48
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ldu 17,8(3) # offset 56
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ldu 18,8(3) # offset 64
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ldu 19,8(3) # offset 72
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ldu 20,8(3) # offset 80
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ldu 21,8(3) # offset 88
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ldu 22,8(3) # offset 96
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ldu 23,8(3) # offset 104
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ldu 24,8(3) # offset 112
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ldu 25,8(3) # offset 120
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ldu 26,8(3) # offset 128
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ldu 27,8(3) # offset 136
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ldu 28,8(3) # offset 144
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ldu 29,8(3) # offset 152
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ldu 30,8(3) # offset 160
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ldu 31,8(3) # offset 168
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ldu 5,8(3) # offset 176
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mtlr 5
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lwzu 5,8(3) # offset 184
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mtcrf 255,5
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#else
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lwz 1,0(3) # offset 0
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lwzu 2,4(3) # offset 4
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lwzu 13,4(3) # offset 8
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lwzu 14,4(3) # offset 12
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lwzu 15,4(3) # offset 16
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lwzu 16,4(3) # offset 20
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lwzu 17,4(3) # offset 24
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lwzu 18,4(3) # offset 28
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lwzu 19,4(3) # offset 32
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lwzu 20,4(3) # offset 36
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lwzu 21,4(3) # offset 40
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lwzu 22,4(3) # offset 44
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lwzu 23,4(3) # offset 48
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lwzu 24,4(3) # offset 52
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lwzu 25,4(3) # offset 56
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lwzu 26,4(3) # offset 60
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lwzu 27,4(3) # offset 64
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lwzu 28,4(3) # offset 68
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lwzu 29,4(3) # offset 72
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lwzu 30,4(3) # offset 76
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lwzu 31,4(3) # offset 80
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#endif
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/* If __SPE__, then add 84 to the offset shown from this point on until
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the end of this function. This difference comes from the fact that
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we restore 22 64-bit registers instead of 22 32-bit registers above. */
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#if !__powerpc64__
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lwzu 5,4(3) # offset 84
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mtlr 5
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lwzu 5,4(3) # offset 88
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mtcrf 255,5
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# one word pad to get floating point aligned on 8 byte boundary
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#endif
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/* Check whether we need to restore FPRs. Checking
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__NO_FPRS__ on its own would be enough for GCC 4.1 and
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above, but older compilers only define _SOFT_FLOAT, so
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check both. */
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#if !defined (__NO_FPRS__) && !defined (_SOFT_FLOAT)
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#if defined (__rtems__) && !defined (__PPC_CPU_E6500__)
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mfmsr 5
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andi. 5,5,0x2000
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beq 1f
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#endif
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/* If __powerpc64__, then add 96 to the offset shown from this point on until
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the end of this function. This difference comes from the fact that
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we restore 23 64-bit registers instead of 23 32-bit registers above and
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we take alignement requirements of floating point and Altivec loads
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into account. */
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lfdu 14,8(3) # offset 96
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lfdu 15,8(3) # offset 104
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lfdu 16,8(3) # offset 112
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lfdu 17,8(3) # offset 120
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lfdu 18,8(3) # offset 128
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lfdu 19,8(3) # offset 136
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lfdu 20,8(3) # offset 144
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lfdu 21,8(3) # offset 152
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lfdu 22,8(3) # offset 160
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lfdu 23,8(3) # offset 168
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lfdu 24,8(3) # offset 176
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lfdu 25,8(3) # offset 184
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lfdu 26,8(3) # offset 192
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lfdu 27,8(3) # offset 200
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lfdu 28,8(3) # offset 208
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lfdu 29,8(3) # offset 216
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lfdu 30,8(3) # offset 224
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lfdu 31,8(3) # offset 232
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1:
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#endif
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#ifdef __ALTIVEC__
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#if defined (__rtems__) && !defined (__PPC_CPU_E6500__)
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mfmsr 5
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andis. 5,5,0x200
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beq 1f
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#endif
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/* restore Altivec vrsave and v20-v31 registers */
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lwzu 5,16(3) # offset 248
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mtspr 256,5 # vrsave
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addi 3,3,8
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lvx 20,0,3 # offset 256
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addi 3,3,16
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lvx 21,0,3 # offset 272
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addi 3,3,16
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lvx 22,0,3 # offset 288
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addi 3,3,16
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lvx 23,0,3 # offset 304
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addi 3,3,16
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lvx 24,0,3 # offset 320
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addi 3,3,16
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lvx 25,0,3 # offset 336
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addi 3,3,16
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lvx 26,0,3 # offset 352
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addi 3,3,16
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lvx 27,0,3 # offset 368
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addi 3,3,16
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lvx 28,0,3 # offset 384
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addi 3,3,16
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lvx 29,0,3 # offset 400
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addi 3,3,16
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lvx 30,0,3 # offset 416
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addi 3,3,16
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lvx 31,0,3 # offset 432
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1:
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#endif
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mr. 3,4
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bclr+ 4,2
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li 3,1
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blr
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FUNC_END(longjmp)
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