208 lines
7.6 KiB
C
208 lines
7.6 KiB
C
/* v850.h -- Header file for NEC V850 opcode table
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Copyright 1996, 1997, 2001, 2003, 2010 Free Software Foundation, Inc.
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Written by J.T. Conklin, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef V850_H
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#define V850_H
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/* The opcode table is an array of struct v850_opcode. */
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struct v850_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned long opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned long mask;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[8];
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/* Which (if any) operand is a memory operand. */
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unsigned int memop;
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/* Target processor(s). A bit field of processors which support
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this instruction. Note a bit field is used as some instructions
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are available on multiple, different processor types, whereas
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other instructions are only available on one specific type. */
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unsigned int processors;
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};
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/* Values for the processors field in the v850_opcode structure. */
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#define PROCESSOR_MASK 0x1f
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#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */
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#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */
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#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
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#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */
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#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
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#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
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#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */
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#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */
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#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */
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#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */
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#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct v850_opcode v850_opcodes[];
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extern const int v850_num_opcodes;
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/* The operands table is an array of struct v850_operand. */
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struct v850_operand
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{
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/* The number of bits in the operand. */
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/* If this value is -1 then the operand's bits are in a discontinous
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distribution in the instruction. */
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int bits;
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/* (bits >= 0): How far the operand is left shifted in the instruction. */
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/* (bits == -1): Bit mask of the bits in the operand. */
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int shift;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (op & ((1 << o->bits) - 1)) << o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned long (* insert)
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(unsigned long instruction, long op, const char ** errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
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if (o->flags & V850_OPERAND_SIGNED)
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op = (op << (32 - o->bits)) >> (32 - o->bits);
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(i is the instruction, o is a pointer to this structure, and op
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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unsigned long (* extract) (unsigned long instruction, int * invalid);
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/* One bit syntax flags. */
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int flags;
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int default_reloc;
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the v850_opcodes table. */
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extern const struct v850_operand v850_operands[];
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/* Values defined for the flags field of a struct v850_operand. */
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/* This operand names a general purpose register. */
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#define V850_OPERAND_REG 0x01
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/* This operand is the ep register. */
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#define V850_OPERAND_EP 0x02
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/* This operand names a system register. */
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#define V850_OPERAND_SRG 0x04
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/* Prologue eilogue type instruction, V850E specific. */
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#define V850E_OPERAND_REG_LIST 0x08
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/* This operand names a condition code used in the setf instruction. */
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#define V850_OPERAND_CC 0x10
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#define V850_OPERAND_FLOAT_CC 0x20
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/* This operand names a vector purpose register. */
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#define V850_OPERAND_VREG 0x40
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/* 16 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE16 0x80
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/* hi16 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE16HI 0x100
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/* 23 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE23 0x200
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/* 32 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE32 0x400
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/* This is a relaxable operand. Only used for D9->D22 branch relaxing
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right now. We may need others in the future (or maybe handle them like
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promoted operands on the mn10300?). */
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#define V850_OPERAND_RELAX 0x800
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/* This operand takes signed values. */
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#define V850_OPERAND_SIGNED 0x1000
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/* This operand is a displacement. */
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#define V850_OPERAND_DISP 0x2000
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/* This operand is a PC displacement. */
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#define V850_PCREL 0x4000
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/* The register specified must be even number. */
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#define V850_REG_EVEN 0x8000
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/* The register specified must not be r0. */
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#define V850_NOT_R0 0x20000
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/* The register specified must not be 0. */
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#define V850_NOT_IMM0 0x40000
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/* The condition code must not be SA CONDITION. */
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#define V850_NOT_SA 0x80000
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/* The operand has '!' prefix. */
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#define V850_OPERAND_BANG 0x100000
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/* The operand has '%' prefix. */
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#define V850_OPERAND_PERCENT 0x200000
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extern int v850_msg_is_out_of_range (const char * msg);
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#endif /* V850_H */
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