Move AHCI Port to use volatile.
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741b605a1c
commit
0024e38412
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@ -127,7 +127,7 @@ impl AhciController {
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.unwrap()
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.unwrap()
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};
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};
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let sata_status = port.sata_status;
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let sata_status = port.sata_status.read();
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if (sata_status.device_detection() != AhciDeviceDetection::CommunicationEstablished)
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if (sata_status.device_detection() != AhciDeviceDetection::CommunicationEstablished)
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|| (sata_status.interface_power_management()
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|| (sata_status.interface_power_management()
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!= AhciInterfacePowerManagement::Active)
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!= AhciInterfacePowerManagement::Active)
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@ -238,25 +238,8 @@ struct PortController<'a> {
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impl<'a> PortController<'a> {
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impl<'a> PortController<'a> {
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fn new(ahci_port_hba: &'a mut AhciPortHba) -> Result<Self, ZError> {
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fn new(ahci_port_hba: &'a mut AhciPortHba) -> Result<Self, ZError> {
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let sata_status = ahci_port_hba.sata_status;
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assert_eq!(
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sata_status.device_detection(),
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AhciDeviceDetection::CommunicationEstablished
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);
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assert_eq!(
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sata_status.interface_power_management(),
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AhciInterfacePowerManagement::Active,
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);
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let (command_structures, command_paddr) = MemoryRegion::contiguous_physical(0x2500)?;
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let (command_structures, command_paddr) = MemoryRegion::contiguous_physical(0x2500)?;
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ahci_port_hba.command_list_base = command_paddr;
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ahci_port_hba.init(command_paddr, command_paddr + 0x400);
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ahci_port_hba.fis_base = command_paddr + 0x400;
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ahci_port_hba.interrupt_enable = AhciPortInterruptEnable::from_bits(0xFFFF_FFFF);
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// Overwrite all errors.
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ahci_port_hba.sata_error = AhciSataError::from_bits(0xFFFF_FFFF);
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let command = ahci_port_hba.command;
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ahci_port_hba.command = command.with_fis_recieve_enable(true).with_start(true);
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let mut controller = Self {
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let mut controller = Self {
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ahci_port_hba,
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ahci_port_hba,
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@ -276,7 +259,7 @@ impl<'a> PortController<'a> {
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}
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}
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pub fn identify(&mut self) -> Result<(), ZError> {
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pub fn identify(&mut self) -> Result<(), ZError> {
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if self.ahci_port_hba.signature == 0x101 {
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if self.ahci_port_hba.signature.read() == 0x101 {
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let sector_size = self.sector_size.clone();
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let sector_size = self.sector_size.clone();
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let sector_cnt = self.sector_cnt.clone();
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let sector_cnt = self.sector_cnt.clone();
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let callback = move |c: &Command| {
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let callback = move |c: &Command| {
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@ -307,7 +290,7 @@ impl<'a> PortController<'a> {
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};
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};
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self.issue_command(Arc::from(Command::identify(Box::new(callback))?))?;
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self.issue_command(Arc::from(Command::identify(Box::new(callback))?))?;
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} else {
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} else {
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let sig = self.ahci_port_hba.signature;
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let sig = self.ahci_port_hba.signature.read();
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mammoth::debug!("Skipping non-sata sig: {:#0x}", sig);
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mammoth::debug!("Skipping non-sata sig: {:#0x}", sig);
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}
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}
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Ok(())
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Ok(())
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@ -327,7 +310,7 @@ impl<'a> PortController<'a> {
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self.command_list()[slot].command =
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self.command_list()[slot].command =
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(size_of::<HostToDeviceRegisterFis>() as u16 / 4) & 0x1F;
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(size_of::<HostToDeviceRegisterFis>() as u16 / 4) & 0x1F;
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self.command_list()[slot].command |= 1 << 7;
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self.command_list()[slot].command |= 1 << 7;
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self.ahci_port_hba.command_issue |= 1 << slot;
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self.ahci_port_hba.issue_command(slot);
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Ok(())
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Ok(())
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}
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}
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@ -373,7 +356,7 @@ impl<'a> PortController<'a> {
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}
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}
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fn handle_interrupt(&mut self) {
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fn handle_interrupt(&mut self) {
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let int_status = self.ahci_port_hba.interrupt_status;
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let int_status = self.ahci_port_hba.interrupt_status.read();
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if int_status.device_to_host_register_fis_interrupt() {
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if int_status.device_to_host_register_fis_interrupt() {
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assert_eq!(
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assert_eq!(
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self.recieved_fis().device_to_host_register_fis.fis_type as u8,
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self.recieved_fis().device_to_host_register_fis.fis_type as u8,
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@ -391,12 +374,14 @@ impl<'a> PortController<'a> {
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);
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);
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}
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}
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self.ahci_port_hba.interrupt_status =
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self.ahci_port_hba.interrupt_status.write(
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AhciPortInterruptStatus::new().with_device_to_host_register_fis_interrupt(true);
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AhciPortInterruptStatus::new().with_device_to_host_register_fis_interrupt(true),
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);
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}
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}
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if int_status.pio_setup_fis_interrupt() {
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if int_status.pio_setup_fis_interrupt() {
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self.ahci_port_hba.interrupt_status =
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self.ahci_port_hba
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AhciPortInterruptStatus::new().with_pio_setup_fis_interrupt(true);
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.interrupt_status
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.write(AhciPortInterruptStatus::new().with_pio_setup_fis_interrupt(true));
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}
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}
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for i in 0..32 {
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for i in 0..32 {
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@ -407,7 +392,7 @@ impl<'a> PortController<'a> {
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// FIXME: This could cause a race condition when issuing a command if a different
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// FIXME: This could cause a race condition when issuing a command if a different
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// interrupt triggers between us setting the command in the command slot and
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// interrupt triggers between us setting the command in the command slot and
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// actually issuing the command.
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// actually issuing the command.
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if (self.ahci_port_hba.command_issue & int_offset) != int_offset {
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if (self.ahci_port_hba.command_issue.read() & int_offset) != int_offset {
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if let Some(_) = &self.command_slots[i] {
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if let Some(_) = &self.command_slots[i] {
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self.finish_command(i);
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self.finish_command(i);
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self.command_slots[i] = None;
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self.command_slots[i] = None;
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@ -1,4 +1,5 @@
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use bitfield_struct::bitfield;
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use bitfield_struct::bitfield;
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use mammoth::mem::Volatile;
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#[bitfield(u32)]
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#[bitfield(u32)]
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pub struct AhciPortInterruptStatus {
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pub struct AhciPortInterruptStatus {
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@ -380,24 +381,55 @@ pub struct AhciDeviceSleep {
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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#[repr(C, packed)]
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#[repr(C)]
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pub struct AhciPortHba {
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pub struct AhciPortHba {
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pub command_list_base: u64,
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pub command_list_base: Volatile<u64>,
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pub fis_base: u64,
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pub fis_base: Volatile<u64>,
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pub interrupt_status: AhciPortInterruptStatus,
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pub interrupt_status: Volatile<AhciPortInterruptStatus>,
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pub interrupt_enable: AhciPortInterruptEnable,
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pub interrupt_enable: Volatile<AhciPortInterruptEnable>,
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pub command: AhciPortCommandAndStatus,
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pub command: Volatile<AhciPortCommandAndStatus>,
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__: u32,
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__: Volatile<u32>,
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pub task_file_data: AhciPortTaskFileData,
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pub task_file_data: Volatile<AhciPortTaskFileData>,
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pub signature: u32,
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pub signature: Volatile<u32>,
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pub sata_status: AhciSataStatus,
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pub sata_status: Volatile<AhciSataStatus>,
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pub sata_control: AhciSataControl,
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pub sata_control: Volatile<AhciSataControl>,
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pub sata_error: AhciSataError,
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pub sata_error: Volatile<AhciSataError>,
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pub sata_active: u32,
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pub sata_active: Volatile<u32>,
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pub command_issue: u32,
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pub command_issue: Volatile<u32>,
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pub sata_notification: u32,
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pub sata_notification: Volatile<u32>,
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pub fis_based_switching_ctl: AhciFisBasedSwitchingControl,
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pub fis_based_switching_ctl: Volatile<AhciFisBasedSwitchingControl>,
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pub device_sleep: AhciDeviceSleep,
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pub device_sleep: Volatile<AhciDeviceSleep>,
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}
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}
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const _: () = assert!(size_of::<AhciPortHba>() == 0x48);
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const _: () = assert!(size_of::<AhciPortHba>() == 0x48);
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impl AhciPortHba {
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pub fn init(&mut self, command_list_phys: u64, fis_phys: u64) {
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let sata_status = self.sata_status.read();
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assert_eq!(
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sata_status.device_detection(),
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AhciDeviceDetection::CommunicationEstablished
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);
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assert_eq!(
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sata_status.interface_power_management(),
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AhciInterfacePowerManagement::Active,
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);
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self.command_list_base.write(command_list_phys);
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self.fis_base.write(fis_phys);
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self.interrupt_enable
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.write(AhciPortInterruptEnable::from_bits(0xFFFF_FFFF));
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// Overwrite all errors.
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self.sata_error.write(AhciSataError::from_bits(0xFFFF_FFFF));
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self.command.update(|command| {
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*command = command.with_fis_recieve_enable(true).with_start(true);
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});
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}
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pub fn issue_command(&mut self, slot: usize) {
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assert!(slot < 32);
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self.command_issue.update(|ci| *ci |= 1 << slot);
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}
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}
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