Add the Denali disk driver.
Begin enumerating information from the PCI structure and HBA AHCI structures. Currently the PCI structure address is hardcoded but it should be passed via a capability from the init process in the future.
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47e3d11060
commit
30bb10207e
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@ -22,7 +22,7 @@ set(QEMU_CMD qemu-system-x86_64 -machine q35 -d guest_errors -m 1G -serial stdio
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add_custom_command(
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OUTPUT disk.img
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COMMAND sudo sh ../scripts/build_image.sh disk.img
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DEPENDS zion yellowstone test2
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DEPENDS zion yellowstone denali
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USES_TERMINAL
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)
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@ -10,3 +10,11 @@ void dbgln(const char* fmt, ...);
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void check(uint64_t);
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void crash(const char*, z_err_t);
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#define RET_ERR(expr) \
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{ \
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z_err_t _tmp_err = expr; \
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if (_tmp_err != Z_OK) { \
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return _tmp_err; \
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} \
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}
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@ -38,6 +38,6 @@ cp ../zion/boot/limine.cfg efi/
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cp zion/zion efi/
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mkdir -p efi/sys
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cp sys/yellowstone/yellowstone efi/sys/yellowstone
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cp sys/test2 efi/sys/test2
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cp sys/denali/denali efi/sys/denali
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chown drew:drew $1
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@ -1,16 +1,5 @@
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set(CMAKE_SHARED_LIBRARY_LINK_CXX_FLAGS "")
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add_subdirectory(yellowstone)
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add_subdirectory(denali)
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add_executable(test2
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test2.cpp)
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target_link_libraries(test2
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cxx
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mammoth_lib)
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set_target_properties(test2
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PROPERTIES
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COMPILE_FLAGS "${CMAKE_CXX_FLAGS} ${BASE_COMPILE_FLAGS}"
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LINK_FLAGS "${CMAKE_EXE_LINK_FLAGS} ${BASE_LINK_FLAGS}"
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)
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@ -3,3 +3,4 @@
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Current Processes;
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- **yellowstone**: System Initialization
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- **denali**: SATA ACHI Disk Driver
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@ -0,0 +1,17 @@
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add_executable(denali
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ahci/ahci_driver.cpp
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denali.cpp)
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target_include_directories(denali
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PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
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target_link_libraries(denali
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cxx
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mammoth_lib
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)
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set_target_properties(denali PROPERTIES
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COMPILE_FLAGS "${CMAKE_CXX_FLAGS} ${BASE_COMPILE_FLAGS}"
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LINK_FLAGS "${CMAKE_EXE_LINK_FLAGS} ${BASE_LINK_FLAGS}"
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)
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@ -0,0 +1,149 @@
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#include "ahci/ahci_driver.h"
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#include <mammoth/debug.h>
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#include <stdint.h>
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#include <zcall.h>
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namespace {
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const uint64_t kSataPciPhys = 0xB00FA000;
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const uint64_t kPciSize = 0x1000;
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} // namespace
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z_err_t AhciDriver::Init() {
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RET_ERR(LoadPciDeviceHeader());
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dbgln("ABAR: %x", pci_device_header_->abar);
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RET_ERR(LoadHbaRegisters());
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dbgln("Version: %x", ahci_hba_->version);
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DumpCapabilities();
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DumpPorts();
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return Z_OK;
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}
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void AhciDriver::DumpCapabilities() {
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dbgln("AHCI Capabilities:");
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uint32_t caps = ahci_hba_->capabilities;
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dbgln("Num Ports: %u", (caps & 0x1F) + 1);
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dbgln("Num Command Slots: %u", (caps & 0x1F00) >> 8);
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if (caps & 0x20) {
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dbgln("External SATA");
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}
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if (caps & 0x40) {
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dbgln("Enclosure Management");
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}
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if (caps & 0x80) {
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dbgln("Command Completion Coalescing");
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}
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if (caps & 0x2000) {
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dbgln("Partial State Capable");
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}
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if (caps & 0x4000) {
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dbgln("Slumber state capable");
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}
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if (caps & 0x8000) {
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dbgln("PIO Multiple DRQ Block");
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}
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if (caps & 0x1'0000) {
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dbgln("FIS-Based Switching");
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}
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if (caps & 0x2'0000) {
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dbgln("Port Multiplier");
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}
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if (caps & 0x4'0000) {
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dbgln("AHCI mode only");
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}
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dbgln("Speed support: %u", (caps & 0xF0'0000) >> 20);
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if (caps & 0x100'0000) {
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dbgln("Command list override");
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}
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if (caps & 0x200'0000) {
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dbgln("Activity LED");
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}
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if (caps & 0x400'0000) {
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dbgln("Aggresive link power management");
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}
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if (caps & 0x800'0000) {
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dbgln("Staggered spin up");
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}
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if (caps & 0x1000'0000) {
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dbgln("Mechanical Switch Presence");
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}
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if (caps & 0x2000'0000) {
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dbgln("SNotification Register");
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}
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if (caps & 0x4000'0000) {
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dbgln("Native Command Queueing");
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}
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if (caps & 0x8000'0000) {
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dbgln("64bit Addressing");
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}
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// Secondary.
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caps = ahci_hba_->capabilities_ext;
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if (caps & 0x1) {
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dbgln("BIOS/OS handoff");
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}
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if (caps & 0x2) {
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dbgln("NVMHCI Present");
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}
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if (caps & 0x4) {
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dbgln("Auto partial to slumber tranisitions");
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}
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if (caps & 0x8) {
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dbgln("Device sleep");
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}
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if (caps & 0x10) {
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dbgln("Aggressive device sleep management");
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}
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}
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void AhciDriver::DumpPorts() {
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dbgln("Ports implemented %x", ahci_hba_->port_implemented);
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uint64_t port_index = 0;
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uint32_t ports_implemented = ahci_hba_->port_implemented;
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while (ports_implemented) {
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if (!(ports_implemented & 0x1)) {
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ports_implemented >>= 1;
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port_index++;
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * port_index);
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AhciPort* port = reinterpret_cast<AhciPort*>(port_addr);
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dbgln("");
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dbgln("Port %u:", port_index);
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dbgln("Comlist: %lx", port->command_list_base);
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dbgln("FIS: %lx", port->fis_base);
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dbgln("Command: %x", port->command);
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dbgln("Signature: %x", port->signature);
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dbgln("SATA status: %x", port->sata_status);
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ports_implemented >>= 1;
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port_index++;
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}
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}
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z_err_t AhciDriver::LoadPciDeviceHeader() {
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uint64_t vmmo_cap;
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RET_ERR(ZMemoryObjectCreatePhysical(kSataPciPhys, kPciSize, &vmmo_cap));
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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pci_device_header_ = reinterpret_cast<PciDeviceHeader*>(vaddr);
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return Z_OK;
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}
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z_err_t AhciDriver::LoadHbaRegisters() {
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uint64_t vmmo_cap;
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RET_ERR(
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ZMemoryObjectCreatePhysical(pci_device_header_->abar, 0x1100, &vmmo_cap));
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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ahci_hba_ = reinterpret_cast<AhciHba*>(vaddr);
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return Z_OK;
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}
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@ -0,0 +1,76 @@
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#pragma once
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#include <zerrors.h>
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struct PciDeviceHeader {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command_reg;
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uint16_t status_reg;
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uint8_t revision;
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uint8_t prog_interface;
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uint8_t subclass;
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uint8_t class_code;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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uint32_t bars[5];
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uint32_t abar;
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uint32_t subsystem_id;
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uint32_t expansion_rom;
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uint8_t cap_ptr;
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uint8_t reserved[7];
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} __attribute__((packed));
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struct AhciHba {
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uint32_t capabilities;
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uint32_t global_host_control;
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uint32_t interrupt_status;
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uint32_t port_implemented;
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uint32_t version;
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uint32_t ccc_ctl; // 0x14, Command completion coalescing control
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uint32_t ccc_pts; // 0x18, Command completion coalescing ports
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uint32_t em_loc; // 0x1C, Enclosure management location
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uint32_t em_ctl; // 0x20, Enclosure management control
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uint32_t capabilities_ext;
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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};
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struct AhciPort {
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uint64_t command_list_base;
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uint64_t fis_base;
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uint32_t interrupt_status;
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uint32_t interrupt_enable;
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uint32_t command;
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uint32_t reserved;
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uint32_t task_file_data;
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uint32_t signature;
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uint32_t sata_status;
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uint32_t sata_control;
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uint32_t sata_error;
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uint32_t sata_active;
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uint32_t command_issue;
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uint32_t sata_notification;
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uint32_t fis_based_switching_ctl;
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uint32_t device_sleep;
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};
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class AhciDriver {
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public:
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z_err_t Init();
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void DumpCapabilities();
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void DumpPorts();
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private:
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PciDeviceHeader* pci_device_header_ = nullptr;
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AhciHba* ahci_hba_ = nullptr;
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z_err_t LoadPciDeviceHeader();
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z_err_t LoadHbaRegisters();
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};
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@ -0,0 +1,8 @@
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#include <stdint.h>
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#include "ahci/ahci_driver.h"
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int main(uint64_t bootstrap_cap) {
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AhciDriver driver;
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return driver.Init();
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}
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@ -1,28 +0,0 @@
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#include <mammoth/channel.h>
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#include <mammoth/debug.h>
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#include <mammoth/thread.h>
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#include <stdlib.h>
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void thread_entry(void* a) {
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dbgln("In thread");
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dbgln(static_cast<const char*>(a));
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}
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int main(uint64_t bootstrap_cap) {
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dbgln("Main thread");
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const char* a = "a";
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const char* b = "bee";
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const char* c = "cee";
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const char* d = "dee";
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Thread t1(thread_entry, a);
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Thread t2(thread_entry, b);
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uint64_t size = 10;
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char* buff = new char[size];
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Channel c1;
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c1.adopt_cap(bootstrap_cap);
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check(c1.ReadStr(buff, &size));
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dbgln(buff);
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return 0;
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}
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@ -7,4 +7,4 @@ TIMEOUT=0
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KERNEL_PATH=boot:///zion
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MODULE_PATH=boot:///sys/yellowstone
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MODULE_PATH=boot:///sys/test2
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MODULE_PATH=boot:///sys/denali
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@ -123,7 +123,7 @@ void LoadInitProgram() {
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uint64_t entry = LoadElfProgram(
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*proc, reinterpret_cast<uint64_t>(init_prog.address), init_prog.size);
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const limine_file& prog2 = GetInitProgram("/sys/test2");
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const limine_file& prog2 = GetInitProgram("/sys/denali");
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RefPtr<MemoryObject> prog2_vmmo = MakeRefCounted<MemoryObject>(prog2.size);
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prog2_vmmo->CopyBytesToObject(reinterpret_cast<uint64_t>(prog2.address),
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prog2.size);
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