[PCI] Improved MSI Comments for my future self.

rust/lib/pci/src/device.rs

@@ -67,21 +67,30 @@ impl PciDevice {
                 .unwrap()
         };
 
-        mammoth::debug!("MSI Cap: {:#x?}", msi_cap);
-
         let control = msi_cap.msi_control;
-        assert!(control.capable_address_64());
-        assert!(control.multi_message_capable() == 0);
+        assert!(
+            control.capable_address_64(),
+            "We don't handle the non-64bit case for MSI yet."
+        );
+        assert!(
+            control.multi_message_capable() == 0,
+            "We don't yet handle multi-message capable devices."
+        );
 
         // FIXME: These probably need to be volatile writes.
         let header: &mut PciDeviceHeader = self.memory_region.as_mut();
         header.command = header.command.with_interrupt_disable(true);
         msi_cap.msi_control = control.with_msi_enable(true);
+
+        // For setting addr and data field, see intel ref
+        // Vol 3. Section 11.11
+        // TODO: This is hardcoded to APIC 0 currently.
         msi_cap.msi_addr_lower = 0xFEE00000;
         msi_cap.msi_addr_upper_or_data = 0x0;
 
         let (cap, irq_num) = syscall::register_msi_irq()?;
 
+        // TODO: Do we need to set the specific level triggering options for this?
         msi_cap.msi_data_if_64 = irq_num as u32;
 
         Ok(cap)