Cleanup AHCI Ident a bit and reduce logging
This commit is contained in:
parent
72885190e9
commit
b8b6576b7f
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@ -35,7 +35,7 @@ struct PciMsiCap {
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uint8_t reserved;
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uint64_t message_address;
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uint16_t message_data;
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};
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} __attribute__((packed));
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struct AhciHba {
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uint32_t capabilities;
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@ -90,7 +90,7 @@ struct PhysicalRegionDescriptor {
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// 21:0 is byte count
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// 31 is Interrupt on Completion
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uint32_t byte_count;
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};
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} __attribute__((packed));
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struct CommandTable {
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uint8_t command_fis[64];
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@ -110,9 +110,73 @@ typedef enum {
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FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host
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} FIS_TYPE;
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struct DmaFis {};
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struct DmaFis {
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_DMA_SETUP
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 1; // Reserved
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uint8_t d : 1; // Data transfer direction, 1 - device to host
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uint8_t i : 1; // Interrupt bit
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uint8_t a : 1; // Auto-activate. Specifies if DMA Activate FIS is needed
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uint8_t rsved[2]; // Reserved
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// DWORD 1&2
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uint64_t DMAbufferID; // DMA Buffer Identifier. Used to Identify DMA buffer
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// in host memory. SATA Spec says host specific and not
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// in Spec. Trying AHCI spec might work.
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// DWORD 3
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uint32_t rsvd; // More reserved
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// DWORD 4
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uint32_t DMAbufOffset; // Byte offset into buffer. First 2 bits must be 0
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// DWORD 5
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uint32_t TransferCount; // Number of bytes to transfer. Bit 0 must be 0
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// DWORD 6
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uint32_t resvd; // Reserved
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} __attribute__((packed));
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struct PioSetupFis {
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_PIO_SETUP
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uint8_t pmport : 4; // Port multiplier
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uint8_t rsv0 : 1; // Reserved
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uint8_t d : 1; // Data transfer direction, 1 - device to host
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uint8_t i : 1; // Interrupt bit
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uint8_t rsv1 : 1;
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uint8_t status; // Status register
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uint8_t error; // Error register
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t rsv2; // Reserved
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// DWORD 3
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uint8_t countl; // Count register, 7:0
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uint8_t counth; // Count register, 15:8
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uint8_t rsv3; // Reserved
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uint8_t e_status; // New value of status register
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// DWORD 4
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uint16_t tc; // Transfer count
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uint8_t rsv4[2]; // Reserved
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} __attribute__((packed));
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struct PioSetupFis {};
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struct HostToDeviceRegisterFis {
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uint8_t fis_type; // FIS_TYPE_REG_H2D
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uint8_t pmp_and_c;
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@ -138,9 +202,36 @@ struct HostToDeviceRegisterFis {
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// DWORD 4
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uint32_t reserved; // Reserved
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};
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struct DeviceToHostRegisterFis {};
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struct SetDeviceBitsFis {};
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} __attribute__((packed));
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struct DeviceToHostRegisterFis {
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// DWORD 0
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uint8_t fis_type; // FIS_TYPE_REG_D2H
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uint8_t pmport_and_i;
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uint8_t status; // Status register
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uint8_t error; // Error register
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t reserved1;
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// DWORD 3
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uint16_t count;
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uint16_t reserved2;
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uint32_t reserved3;
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} __attribute__((packed));
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struct SetDeviceBitsFis {
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} __attribute__((packed));
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struct ReceivedFis {
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DmaFis dma_fis;
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@ -4,6 +4,12 @@
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#include <string.h>
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#include <zcall.h>
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namespace {
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void HandleIdent(AhciDevice* dev) { dev->HandleIdentify(); }
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} // namespace
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AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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if ((port_struct_->sata_status & 0x103) != 0x103) {
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return;
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@ -15,27 +21,30 @@ AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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crash("Non adjacent cl & fis", Z_ERR_UNIMPLEMENTED);
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}
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check(ZMemoryObjectCreatePhysical(cl_page, 0x1000, &vmmo_cap_));
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uint64_t vaddr;
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check(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap_, &vaddr));
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command_structures_ = MappedMemoryRegion::DirectPhysical(cl_page, 0x1000);
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uint64_t cl_off = port_struct_->command_list_base & 0xFFF;
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command_list_ = reinterpret_cast<CommandList*>(vaddr + cl_off);
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command_list_ =
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reinterpret_cast<CommandList*>(command_structures_.vaddr() + cl_off);
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uint64_t fis_off = port_struct_->fis_base & 0xFFF;
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received_fis_ = reinterpret_cast<ReceivedFis*>(vaddr + fis_off);
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received_fis_ =
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reinterpret_cast<ReceivedFis*>(command_structures_.vaddr() + fis_off);
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// FIXME: Hacky
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uint64_t ct_off =
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command_list_->command_headers[0].command_table_base_addr & 0xFFF;
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command_table_ = reinterpret_cast<CommandTable*>(vaddr + ct_off);
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command_table_ =
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reinterpret_cast<CommandTable*>(command_structures_.vaddr() + ct_off);
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port_struct_->interrupt_status = 0;
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port_struct_->interrupt_enable = 0xFFFFFFFF;
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if (port_struct_->signature == 0x101) {
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SendIdentify();
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}
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}
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z_err_t AhciDevice::SendIdentify(uint16_t** result) {
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z_err_t AhciDevice::SendIdentify() {
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HostToDeviceRegisterFis fis{
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.fis_type = FIS_TYPE_REG_H2D,
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.pmp_and_c = 0x80,
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@ -64,22 +73,24 @@ z_err_t AhciDevice::SendIdentify(uint16_t** result) {
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memcpy(command_table_->command_fis, &fis, sizeof(fis));
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port_struct_->command_issue |= 1;
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commands_[0].region = MappedMemoryRegion::ContiguousPhysical(512);
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commands_[0].callback = HandleIdent;
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uint64_t vmmo_cap, paddr;
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RET_ERR(ZMemoryObjectCreateContiguous(512, &vmmo_cap, &paddr));
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command_table_->prds[0].region_address = paddr;
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command_table_->prds[0].region_address = commands_[0].region.paddr();
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command_table_->prds[0].byte_count = 512;
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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*result = reinterpret_cast<uint16_t*>(vaddr);
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port_struct_->command_issue |= 1;
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commands_issued_ |= 1;
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return Z_OK;
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}
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void AhciDevice::HandleIdentify() {
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dbgln("Handling Idenify");
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uint16_t* ident = reinterpret_cast<uint16_t*>(commands_[0].region.vaddr());
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dbgln("Ident: %x", ident[0]);
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}
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void AhciDevice::DumpInfo() {
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dbgln("Comlist: %lx", port_struct_->command_list_base);
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dbgln("FIS: %lx", port_struct_->fis_base);
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@ -88,7 +99,6 @@ void AhciDevice::DumpInfo() {
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dbgln("SATA status: %x", port_struct_->sata_status);
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dbgln("Int status: %x", port_struct_->interrupt_status);
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dbgln("Int enable: %x", port_struct_->interrupt_enable);
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dbgln("Int enable: %x", port_struct_->interrupt_enable);
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// Just dump one command info for now.
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for (uint64_t i = 0; i < 1; i++) {
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@ -105,5 +115,36 @@ void AhciDevice::HandleIrq() {
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// FIXME: Probably only clear the interrupts we know how to handle.
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port_struct_->interrupt_status = int_status;
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dbgln("int receieved: %x", int_status);
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uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
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for (uint64_t i = 0; i < 32; i++) {
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if (commands_finished & (1 << i)) {
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commands_[i].callback(this);
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commands_issued_ &= ~(1 << i);
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}
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}
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// TODO: Do something with this information.
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if (int_status & 0x1) {
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// Device to host.
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DeviceToHostRegisterFis& fis = received_fis_->device_to_host_register_fis;
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if (fis.fis_type != FIS_TYPE_REG_D2H) {
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dbgln("BAD FIS TYPE (exp,act): %x, %x", FIS_TYPE_REG_D2H, fis.fis_type);
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return;
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}
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if (fis.error) {
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dbgln("D2H err: %x", fis.error);
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}
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}
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if (int_status & 0x2) {
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// PIO.
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PioSetupFis& fis = received_fis_->pio_set_fis;
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if (fis.fis_type != FIS_TYPE_PIO_SETUP) {
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dbgln("BAD FIS TYPE (exp,act): %x, %x", FIS_TYPE_PIO_SETUP, fis.fis_type);
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return;
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}
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if (fis.error) {
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dbgln("PIO err: %x", fis.error);
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}
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}
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}
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@ -1,5 +1,6 @@
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#pragma once
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#include <mammoth/memory_region.h>
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#include <zerrors.h>
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#include "ahci/ahci.h"
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@ -12,18 +13,26 @@ class AhciDevice {
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void DumpInfo();
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bool IsInit() { return port_struct_ != nullptr && vmmo_cap_ != 0; }
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bool IsInit() { return port_struct_ != nullptr && command_structures_; }
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// Result will point to a 512 byte (256 word array).
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z_err_t SendIdentify(uint16_t** result);
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z_err_t SendIdentify();
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void HandleIdentify();
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void HandleIrq();
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private:
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AhciPort* port_struct_ = nullptr;
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uint64_t vmmo_cap_ = 0;
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MappedMemoryRegion command_structures_;
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CommandList* command_list_ = nullptr;
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ReceivedFis* received_fis_ = nullptr;
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CommandTable* command_table_ = nullptr;
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struct Command {
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typedef void (*Callback)(AhciDevice*);
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MappedMemoryRegion region;
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Callback callback;
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};
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Command commands_[32];
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uint32_t commands_issued_ = 0;
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};
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@ -23,17 +23,13 @@ void interrupt_thread(void* void_driver) {
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z_err_t AhciDriver::Init() {
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RET_ERR(LoadPciDeviceHeader());
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RET_ERR(LoadCapabilities());
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dbgln("ABAR: %x", pci_device_header_->abar);
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dbgln("Interrupt line: %x", pci_device_header_->interrupt_line);
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dbgln("Interrupt pin: %x", pci_device_header_->interrupt_pin);
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// RET_ERR(LoadCapabilities());
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RET_ERR(RegisterIrq());
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RET_ERR(LoadHbaRegisters());
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dbgln("Version: %x", ahci_hba_->version);
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ahci_hba_->global_host_control |= kGhc_InteruptEnable;
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RET_ERR(LoadDevices());
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DumpCapabilities();
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DumpPorts();
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// DumpCapabilities();
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// DumpPorts();
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return Z_OK;
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}
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@ -41,8 +37,6 @@ void AhciDriver::DumpCapabilities() {
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dbgln("AHCI Capabilities:");
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uint32_t caps = ahci_hba_->capabilities;
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dbgln("Num Ports: %u", (caps & 0x1F) + 1);
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dbgln("Num Command Slots: %u", ((caps & 0x1F00) >> 8) + 1);
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if (caps & 0x20) {
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dbgln("External SATA");
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}
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@ -134,21 +128,18 @@ void AhciDriver::InterruptLoop() {
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while (true) {
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uint64_t type, bytes, caps;
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check(ZPortRecv(irq_port_cap_, 0, 0, 0, 0, &type, &bytes, &caps));
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for (uint64_t i = 0; i < 6; i++) {
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if (devices_[i].IsInit()) {
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for (uint64_t i = 0; i < 32; i++) {
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if (devices_[i].IsInit() && (ahci_hba_->interrupt_status & (1 << i))) {
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devices_[i].HandleIrq();
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ahci_hba_->interrupt_status &= ~(1 << i);
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}
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}
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}
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}
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z_err_t AhciDriver::LoadPciDeviceHeader() {
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uint64_t vmmo_cap;
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RET_ERR(ZMemoryObjectCreatePhysical(kSataPciPhys, kPciSize, &vmmo_cap));
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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pci_device_header_ = reinterpret_cast<PciDeviceHeader*>(vaddr);
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pci_region_ = MappedMemoryRegion::DirectPhysical(kSataPciPhys, kPciSize);
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pci_device_header_ = reinterpret_cast<PciDeviceHeader*>(pci_region_.vaddr());
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return Z_OK;
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}
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@ -192,31 +183,23 @@ z_err_t AhciDriver::RegisterIrq() {
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}
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z_err_t AhciDriver::LoadHbaRegisters() {
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uint64_t vmmo_cap;
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RET_ERR(
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ZMemoryObjectCreatePhysical(pci_device_header_->abar, 0x1100, &vmmo_cap));
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ahci_region_ =
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MappedMemoryRegion::DirectPhysical(pci_device_header_->abar, 0x1100);
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ahci_hba_ = reinterpret_cast<AhciHba*>(ahci_region_.vaddr());
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num_ports_ = (ahci_hba_->capabilities & 0x1F) + 1;
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num_commands_ = ((ahci_hba_->capabilities & 0x1F00) >> 8) + 1;
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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ahci_hba_ = reinterpret_cast<AhciHba*>(vaddr);
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return Z_OK;
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}
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z_err_t AhciDriver::LoadDevices() {
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// FIXME: Don't set this up so we hardcode 6 devices.
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for (uint8_t i = 0; i < 6; i++) {
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for (uint8_t i = 0; i < 32; i++) {
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if (!(ahci_hba_->port_implemented & (1 << i))) {
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
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devices_[i] = AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
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if (!devices_[i].IsInit()) {
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continue;
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}
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dbgln("Identify %u", i);
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uint16_t* identify;
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devices_[i].SendIdentify(&identify);
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}
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return Z_OK;
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}
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@ -16,14 +16,20 @@ class AhciDriver {
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void DumpPorts();
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private:
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MappedMemoryRegion pci_region_;
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PciDeviceHeader* pci_device_header_ = nullptr;
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MappedMemoryRegion ahci_region_;
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AhciHba* ahci_hba_ = nullptr;
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AhciDevice devices_[6];
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// TODO: Allocate these dynamically.
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AhciDevice devices_[32];
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Thread irq_thread_;
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uint64_t irq_port_cap_ = 0;
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uint64_t num_ports_;
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uint64_t num_commands_;
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z_err_t LoadPciDeviceHeader();
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z_err_t LoadCapabilities();
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z_err_t RegisterIrq();
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@ -136,7 +136,6 @@ void ParseMcfg(SdtHeader* rsdt) {
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void ParseMadt(SdtHeader* rsdt) {
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#if K_ACPI_DEBUG
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dbgsz(rsdt->signature, 4);
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#endif
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uint64_t max_addr = reinterpret_cast<uint64_t>(rsdt) + rsdt->length;
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MadtHeader* header = reinterpret_cast<MadtHeader*>(rsdt);
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@ -180,6 +179,7 @@ void ParseMadt(SdtHeader* rsdt) {
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entry = reinterpret_cast<MadtEntry*>(reinterpret_cast<uint64_t>(entry) +
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entry->length);
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}
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#endif
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}
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void ParseSdt(SdtHeader* rsdt) {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include "common/port.h"
|
||||
#include "debug/debug.h"
|
||||
|
||||
#define APIC_DEBUG 1
|
||||
#define APIC_DEBUG 0
|
||||
|
||||
namespace {
|
||||
|
||||
|
|
|
|||
|
|
@ -187,7 +187,6 @@ z_err_t ChannelRecv(ZChannelRecvReq* req) {
|
|||
|
||||
z_err_t PortRecv(ZPortRecvReq* req) {
|
||||
auto& proc = gScheduler->CurrentProcess();
|
||||
dbgln("Port cap %u", req->port_cap);
|
||||
auto port_cap = proc.GetCapability(req->port_cap);
|
||||
RET_ERR(ValidateCap(port_cap, Capability::PORT, ZC_READ));
|
||||
|
||||
|
|
@ -199,12 +198,10 @@ z_err_t IrqRegister(ZIrqRegisterReq* req, ZIrqRegisterResp* resp) {
|
|||
auto& proc = gScheduler->CurrentProcess();
|
||||
if (req->irq_num != Z_IRQ_PCI_BASE) {
|
||||
// FIXME: Don't hardcode this nonsense.
|
||||
dbgln("Irq %x", req->irq_num);
|
||||
return Z_ERR_UNIMPLEMENTED;
|
||||
}
|
||||
RefPtr<Port> port = MakeRefCounted<Port>();
|
||||
resp->port_cap = proc.AddCapability(port);
|
||||
dbgln("Port cap %u", resp->port_cap);
|
||||
RegisterPciPort(port);
|
||||
return Z_OK;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue