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No commits in common. "21265e76edf4fa93b8ec1795da4bdd2fc70b79d9" and "e308d8e12031ec77a0252e9b3ac80b451f494b65" have entirely different histories.
21265e76ed
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e308d8e120
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@ -55,20 +55,10 @@ glcr::ErrorCode AhciPort::Identify() {
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ASSIGN_OR_RETURN(auto* sem, IssueCommand(identify));
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sem->Wait();
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uint16_t* ident = reinterpret_cast<uint16_t*>(region.vaddr());
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if (ident[106] & (1 << 12)) {
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sector_size_ = *reinterpret_cast<uint32_t*>(ident + 117);
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} else {
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sector_size_ = 512;
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}
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if (ident[83] & (1 << 10)) {
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lba_count_ = *reinterpret_cast<uint64_t*>(ident + 100);
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} else {
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lba_count_ = *reinterpret_cast<uint32_t*>(ident + 60);
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}
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dbgln("Sector size: {x}", sector_size_);
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dbgln("LBA Count: {x}", lba_count_);
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is_init_ = true;
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uint32_t* sector_size = reinterpret_cast<uint32_t*>(ident + 117);
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dbgln("Sector size: {}", *sector_size);
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uint64_t* lbas = reinterpret_cast<uint64_t*>(ident + 100);
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dbgln("LBA Count: {}", *lbas);
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}
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return glcr::OK;
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}
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@ -166,6 +156,8 @@ void AhciPort::HandleIrq() {
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bool has_error = false;
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if (int_status & kInterrupt_D2H_FIS) {
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dbgln("D2H Received");
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// Device to host.
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volatile DeviceToHostRegisterFis& fis =
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received_fis_->device_to_host_register_fis;
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if (!CheckFisType(FIS_TYPE_REG_D2H, fis.fis_type)) {
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@ -180,10 +172,13 @@ void AhciPort::HandleIrq() {
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}
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}
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if (int_status & kInterrupt_PIO_FIS) {
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dbgln("PIO Received");
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// PIO.
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volatile PioSetupFis& fis = received_fis_->pio_set_fis;
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if (!CheckFisType(FIS_TYPE_PIO_SETUP, fis.fis_type)) {
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return;
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}
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dbgln("Count: {x} {x} {x}", fis.counth, fis.countl, fis.e_status);
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if (fis.error) {
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dbgln("PIO err: {x}", fis.error);
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dbgln("status: {x}", fis.status);
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@ -191,6 +186,7 @@ void AhciPort::HandleIrq() {
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}
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}
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if (int_status & kInterrupt_DMA_FIS) {
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dbgln("DMA Received");
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volatile DmaFis& fis = received_fis_->dma_fis;
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if (!CheckFisType(FIS_TYPE_DMA_SETUP, fis.fis_type)) {
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return;
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@ -198,6 +194,7 @@ void AhciPort::HandleIrq() {
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// TODO: Actually do something with this FIS.
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}
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if (int_status & kInterrupt_DeviceBits_FIS) {
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dbgln("Device Bits Received");
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volatile SetDeviceBitsFis& fis = received_fis_->set_device_bits_fis;
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if (!CheckFisType(FIS_TYPE_DEV_BITS, fis.fis_type)) {
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return;
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@ -20,7 +20,7 @@ class AhciPort {
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void DumpInfo();
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bool IsSata() { return port_struct_->signature == 0x101; }
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bool IsInit() { return is_init_; }
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bool IsInit() { return port_struct_ != nullptr && command_structures_; }
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glcr::ErrorCode Identify();
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@ -43,9 +43,5 @@ class AhciPort {
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glcr::Array<mmth::Semaphore> command_signals_;
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uint32_t commands_issued_ = 0;
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bool is_init_ = false;
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uint64_t lba_count_ = 0;
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uint32_t sector_size_ = 0;
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glcr::ErrorOr<mmth::Semaphore*> IssueCommand(const CommandInfo& command);
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};
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