rust/.cargo/config.toml

@@ -7,4 +7,3 @@ target = "x86_64-acadia-os.json"
 
 [alias]
 test_pc = "test --target=x86_64-unknown-linux-gnu -Z build-std=std --lib"
-

rust/Cargo.lock

@@ -8,17 +8,6 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0c4b4d0bd25bd0b74681c0ad21497610ce1b7c91b1022cd21c80c6fbdd9476b0"
 
-[[package]]
-name = "bitfield-struct"
-version = "0.8.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "de05f8756f1c68937349406d4632ae96ae35901019b5e59c508d9c38c64715fb"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
 [[package]]
 name = "convert_case"
 version = "0.6.0"
@@ -32,7 +21,6 @@ dependencies = [
 name = "denali"
 version = "0.1.0"
 dependencies = [
- "bitfield-struct",
  "mammoth",
  "yellowstone-yunq",
  "yunq",

rust/sys/denali/Cargo.toml

@@ -4,7 +4,6 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies]
-bitfield-struct = "0.8.0"
 mammoth = { path = "../../lib/mammoth" }
 yunq = {path = "../../lib/yunq"}
 

rust/sys/denali/src/ahci/controller.rs

@@ -1,7 +1,5 @@
 use mammoth::mem::MemoryRegion;
 
-use bitfield_struct::bitfield;
-
 #[repr(C, packed)]
 pub struct PciDeviceHeader {
     pub vendor_id: u16,
@@ -18,195 +16,24 @@ pub struct PciDeviceHeader {
     pub bist: u8,
     pub bars: [u32; 5],
     pub abar: u32,
-    __: u32,
+    pub reserved0: u32,
     pub subsystem_id: u32,
     pub expansion_rom: u16,
     pub cap_ptr: u8,
-    ___: [u8; 7],
+    pub reserved1: [u8; 7],
     pub interrupt_line: u8,
     pub interrupt_pin: u8,
     pub min_grant: u8,
     pub max_latency: u8,
 }
 
-const fn increment(val: u8) -> u8 {
-    val + 1
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[repr(u8)]
-enum InterfaceSpeedSupport {
-    Reserved = 0b0000,
-    // 1.5 Gbps
-    Gen1 = 0b0001,
-    // 3 Gbps
-    Gen2 = 0b0010,
-    // 6 Gbps
-    Gen3 = 0b0011,
-    Unknown = 0b1111,
-}
-
-impl InterfaceSpeedSupport {
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0b0000 => Self::Reserved,
-            0b0001 => Self::Gen1,
-            0b0010 => Self::Gen2,
-            0b0011 => Self::Gen3,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[bitfield(u32)]
-pub struct AhciCapabilities {
-    #[bits(5, access = RO, from = increment)]
-    num_ports: u8,
-
-    #[bits(access = RO)]
-    supports_external_sata: bool,
-
-    #[bits(access = RO)]
-    enclosure_management_supported: bool,
-
-    #[bits(access = RO)]
-    command_completed_coalescing_supported: bool,
-
-    #[bits(5, access = RO, from = increment)]
-    num_commands: u8,
-
-    #[bits(access = RO)]
-    partial_state_capable: bool,
-
-    #[bits(access = RO)]
-    slumber_state_capable: bool,
-
-    #[bits(access = RO)]
-    pio_multiple_drq_block: bool,
-
-    #[bits(access = RO)]
-    fis_based_switching_supported: bool,
-
-    #[bits(access = RO)]
-    supports_port_multiplier: bool,
-
-    #[bits(access = RO)]
-    supports_ahci_mode_only: bool,
-
-    __: bool,
-
-    #[bits(4, access = RO)]
-    interface_speed_support: InterfaceSpeedSupport,
-
-    #[bits(access = RO)]
-    supports_command_list_override: bool,
-
-    #[bits(access = RO)]
-    supports_activity_led: bool,
-
-    #[bits(access = RO)]
-    supports_aggressive_link_power_management: bool,
-
-    #[bits(access = RO)]
-    supports_staggered_spin_up: bool,
-
-    #[bits(access = RO)]
-    supports_mechanical_presence_switch: bool,
-
-    #[bits(access = RO)]
-    supports_snotification_register: bool,
-
-    #[bits(access = RO)]
-    supports_native_command_queueing: bool,
-
-    #[bits(access = RO)]
-    supports_64_bit_addressing: bool,
-}
-
-#[bitfield(u32)]
-pub struct AhciGlobalControl {
-    hba_reset: bool,
-    interrupt_enable: bool,
-
-    #[bits(access = RO)]
-    msi_revert_to_single_message: bool,
-
-    #[bits(28)]
-    __: u32,
-
-    ahci_enable: bool,
-}
-
-#[bitfield(u32)]
-pub struct AhciCapabilitiesExtended {
-    #[bits(access = RO)]
-    bios_os_handoff: bool,
-
-    #[bits(access = RO)]
-    nvmhci_present: bool,
-
-    #[bits(access = RO)]
-    automatic_partial_to_slumber_transitions: bool,
-
-    #[bits(access = RO)]
-    supports_device_sleep: bool,
-
-    #[bits(access = RO)]
-    supports_aggressive_device_sleep_management: bool,
-
-    #[bits(27)]
-    __: u32,
-}
-
-#[bitfield(u32)]
-pub struct AhciBiosHandoffControl {
-    bios_owned_semaphore: bool,
-    os_owned_semaphore: bool,
-    smi_on_os_ownership_change_enable: bool,
-    os_ownership_change: bool,
-    bios_busy: bool,
-
-    #[bits(27)]
-    __: u32,
-}
-
-#[derive(Debug)]
-#[repr(C, packed)]
-pub struct AhciHba {
-    pub capabilities: AhciCapabilities,
-    global_host_control: AhciGlobalControl,
-    interrupt_status: u32,
-    port_implemented: u32,
-    version: u32,
-    ccc_ctl: u32, // 0x14, Command completion coalescing control
-    ccc_pts: u32, // 0x18, Command completion coalescing ports
-    em_loc: u32,  // 0x1C, Enclosure management location
-    em_ctl: u32,  // 0x20, Enclosure management control
-    capabilities_ext: AhciCapabilitiesExtended,
-    bohc: AhciBiosHandoffControl,
-}
-
 pub struct AhciController {
     pci_memory: MemoryRegion,
-    hba_memory: MemoryRegion,
 }
 
 impl AhciController {
     pub fn new(pci_memory: MemoryRegion) -> Self {
-        let pci_device_header = unsafe {
+        Self { pci_memory }
-            pci_memory
-                .mut_slice::<u8>()
-                .as_mut_ptr()
-                .cast::<PciDeviceHeader>()
-                .as_mut()
-                .unwrap()
-        };
-        let hba_memory =
-            MemoryRegion::direct_physical(pci_device_header.abar as u64, 0x1100).unwrap();
-        Self {
-            pci_memory,
-            hba_memory,
-        }
     }
 
     pub fn pci_header(&self) -> &mut PciDeviceHeader {
@@ -219,15 +46,4 @@ impl AhciController {
                 .unwrap()
         }
     }
-
-    pub fn ahci_hba(&self) -> &mut AhciHba {
-        unsafe {
-            self.hba_memory
-                .mut_slice::<u8>()
-                .as_mut_ptr()
-                .cast::<AhciHba>()
-                .as_mut()
-                .unwrap()
-        }
-    }
 }

rust/sys/denali/src/ahci/mod.rs

@@ -1,4 +1,3 @@
 mod controller;
-mod port;
 
 pub use controller::AhciController;

rust/sys/denali/src/ahci/port.rs

@@ -1,397 +0,0 @@
-#[bitfield(u32)]
-struct AhciPortInterruptStatus {
-    device_to_host_register_fis_interrupt: bool,
-    pio_setup_fis_interrupt: bool,
-    dma_setup_fis_interrupt: bool,
-    set_device_bits_interrupt: bool,
-    #[bits(access = RO)]
-    unknown_fis_interrupt: bool,
-    descriptor_prossed: bool,
-    #[bits(access = RO)]
-    port_connect_change_status: bool,
-    device_mechanical_presence_status: bool,
-
-    #[bits(14)]
-    __: u32,
-
-    #[bits(access = RO)]
-    phy_rdy_change_status: bool,
-    incorrect_port_multiplier_status: bool,
-    overflow_status: bool,
-
-    __: bool,
-    interface_non_fatal_error_status: bool,
-    interface_fatal_error_status: bool,
-    host_bus_data_error_status: bool,
-    host_bus_fatal_error_status: bool,
-    task_file_error_status: bool,
-    cold_port_detect_status: bool,
-}
-
-#[bitfield(u32)]
-struct AhciPortInterruptEnable {
-    device_to_host_register_fis_enable: bool,
-    pio_setup_fis_enable: bool,
-    dma_setup_fis_enable: bool,
-    set_device_bits_fis_enable: bool,
-    unknown_fis_enable: bool,
-    descriptor_processed_enable: bool,
-    port_change_enable: bool,
-    device_mechanical_presence_enable: bool,
-
-    #[bits(14)]
-    __: u32,
-
-    phy_rdy_change_enable: bool,
-    incorrect_port_multiplier_enable: bool,
-    overflow_enable: bool,
-
-    __: bool,
-
-    interface_non_fatal_error_enable: bool,
-    interface_fatal_error_enable: bool,
-    host_bus_data_error_enable: bool,
-    host_bust_fatal_error_enable: bool,
-    task_file_error_enable: bool,
-    cold_presence_detect_enable: bool,
-}
-
-#[repr(u8)]
-#[derive(Debug)]
-enum InterfaceCommunicationControl {
-    NoOpOrIdle = 0x0,
-    Active = 0x1,
-    Partial = 0x2,
-    Slumber = 0x6,
-    DevSleep = 0x8,
-    Unknown = 0xF,
-}
-
-impl InterfaceCommunicationControl {
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoOpOrIdle,
-            0x1 => Self::Active,
-            0x2 => Self::Partial,
-            0x6 => Self::Slumber,
-            0x8 => Self::DevSleep,
-            _ => Self::Unknown,
-        }
-    }
-
-    const fn into_bits(self) -> u8 {
-        self as _
-    }
-}
-
-#[bitfield(u32)]
-struct AhciPortCommandAndStatus {
-    start: bool,
-    spin_up_device: bool,
-    power_on_device: bool,
-    command_list_overide: bool,
-    fis_recieve_enable: bool,
-
-    #[bits(3)]
-    __: u8,
-
-    #[bits(5, access = RO)]
-    current_command_slot: u8,
-
-    #[bits(access = RO)]
-    mechanical_presence_switch_state: bool,
-    #[bits(access = RO)]
-    fis_receive_running: bool,
-    #[bits(access = RO)]
-    command_list_running: bool,
-    #[bits(access = RO)]
-    cold_presence_state: bool,
-    port_multipler_attached: bool,
-    #[bits(access = RO)]
-    hot_plug_capable_port: bool,
-    #[bits(access = RO)]
-    mechanical_presence_switch_attached_to_port: bool,
-    #[bits(access = RO)]
-    cold_presence_detection: bool,
-    #[bits(access = RO)]
-    external_sata_port: bool,
-    #[bits(access = RO)]
-    fis_base_switch_capable: bool,
-    automatic_partial_to_slumber_transitions_enable: bool,
-    device_is_atapi: bool,
-    drive_led_on_atapi_enable: bool,
-    aggressive_power_link_management_enable: bool,
-    aggressive_slumber_partial: bool,
-
-    #[bits(4)]
-    interface_communication_control: InterfaceCommunicationControl,
-}
-
-#[bitfield(u32)]
-struct AhciPortTaskFileData {
-    #[bits(access = RO)]
-    err_status: bool,
-    #[bits(2, access = RO)]
-    command_specific_status_lo: u8,
-    #[bits(access = RO)]
-    data_transfer_requested: bool,
-    #[bits(3, access = RO)]
-    command_specific_status_hi: u8,
-    #[bits(access = RO)]
-    busy_status: bool,
-
-    #[bits(8, access = RO)]
-    error: u8,
-
-    #[bits(16)]
-    __: u16,
-}
-
-#[derive(Debug)]
-#[repr(u8)]
-enum AhciDeviceDetection {
-    NoDevice = 0x0,
-    NoCommunication = 0x1,
-    CommunicationEstablished = 0x3,
-    OfflineMode = 0x4,
-    Unknown = 0xF,
-}
-
-impl AhciDeviceDetection {
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoDevice,
-            0x1 => Self::NoCommunication,
-            0x3 => Self::CommunicationEstablished,
-            0x4 => Self::OfflineMode,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[derive(Debug)]
-#[repr(u8)]
-enum AhciCurrentInterfaceSpeed {
-    NoDevice = 0x0,
-    Gen1 = 0x1,
-    Gen2 = 0x2,
-    Gen3 = 0x3,
-    Unknown = 0xF,
-}
-
-impl AhciCurrentInterfaceSpeed {
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoDevice,
-            0x1 => Self::Gen1,
-            0x2 => Self::Gen2,
-            0x3 => Self::Gen3,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[derive(Debug)]
-#[repr(u8)]
-enum AhciInterfacePowerManagement {
-    NoDevice = 0x0,
-    Active = 0x1,
-    PartialPower = 0x2,
-    Slumber = 0x6,
-    DevSleep = 0x8,
-    Unknown = 0xF,
-}
-
-impl AhciInterfacePowerManagement {
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoDevice,
-            0x1 => Self::Active,
-            0x2 => Self::PartialPower,
-            0x6 => Self::Slumber,
-            0x8 => Self::DevSleep,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[bitfield(u32)]
-struct AhciSataStatus {
-    #[bits(4, access = RO)]
-    device_detection: AhciDeviceDetection,
-
-    #[bits(4, access = RO)]
-    current_interface_speed: AhciCurrentInterfaceSpeed,
-
-    #[bits(4, access = RO)]
-    interface_power_management: AhciInterfacePowerManagement,
-
-    #[bits(20)]
-    __: u32,
-}
-
-#[derive(Debug)]
-#[repr(u8)]
-enum AhciDeviceDetectionInitialization {
-    NoDevice = 0x0,
-    PerformInterfaceCommunicationInitializationSequence = 0x1,
-    DisableSata = 0x4,
-    Unknown = 0xF,
-}
-
-impl AhciDeviceDetectionInitialization {
-    const fn into_bits(self) -> u8 {
-        self as _
-    }
-
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoDevice,
-            0x1 => Self::PerformInterfaceCommunicationInitializationSequence,
-            0x4 => Self::DisableSata,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[derive(Debug)]
-#[repr(u8)]
-enum AhciSpeedAllowed {
-    NoRestrictions = 0x0,
-    LimitGen1 = 0x1,
-    LimitGen2 = 0x2,
-    LimitGen3 = 0x3,
-    Unknown = 0xF,
-}
-
-impl AhciSpeedAllowed {
-    const fn into_bits(self) -> u8 {
-        self as _
-    }
-
-    const fn from_bits(value: u8) -> Self {
-        match value {
-            0x0 => Self::NoRestrictions,
-            0x1 => Self::LimitGen1,
-            0x2 => Self::LimitGen2,
-            0x3 => Self::LimitGen3,
-            _ => Self::Unknown,
-        }
-    }
-}
-
-#[bitfield(u32)]
-struct AhciSataControl {
-    #[bits(4)]
-    device_detection_initialization: AhciDeviceDetectionInitialization,
-
-    #[bits(4)]
-    speed_allowed: AhciSpeedAllowed,
-
-    partial_transition_disabled: bool,
-    slumber_transition_disabled: bool,
-    devsleep_transition_disabled: bool,
-
-    __: bool,
-
-    #[bits(20)]
-    __: u32,
-}
-
-#[bitfield(u32)]
-struct AhciSataError {
-    recovered_data_integrity_error: bool,
-    recovered_communications_error: bool,
-
-    #[bits(6)]
-    __: u8,
-
-    transient_data_integrity_error: bool,
-    persisten_communication_or_data_integrity_error: bool,
-    protocol_error: bool,
-    internal_error: bool,
-
-    #[bits(4)]
-    __: u8,
-
-    phy_ready_change: bool,
-    phy_internal_error: bool,
-    comm_wake: bool,
-    decode_error: bool,
-    __: bool,
-    crc_error: bool,
-    handshake_error: bool,
-    link_sequence_error: bool,
-    transport_state_transition_error: bool,
-    uknown_fis_type: bool,
-    exchanged: bool,
-
-    #[bits(5)]
-    __: u8,
-}
-
-#[bitfield(u32)]
-struct AhciFisBasedSwitchingControl {
-    enable: bool,
-    device_error_clear: bool,
-
-    #[bits(access = RO)]
-    single_device_error: bool,
-
-    #[bits(5)]
-    __: u8,
-
-    #[bits(4)]
-    device_to_issue: u8,
-
-    #[bits(4, access = RO)]
-    active_device_optimization: u8,
-
-    #[bits(4, access = RO)]
-    device_with_error: u8,
-
-    #[bits(12)]
-    __: u16,
-}
-
-#[bitfield(u32)]
-struct AhciDeviceSleep {
-    aggressive_device_sleep_enable: bool,
-
-    #[bits(access = RO)]
-    device_sleep_present: bool,
-
-    device_sleep_exit_timeout: u8,
-
-    #[bits(5)]
-    minimum_device_sleep_assertion_time: u8,
-
-    #[bits(10)]
-    device_sleep_idle_timeout: u16,
-
-    #[bits(4)]
-    dito_multiplier: u8,
-
-    #[bits(3)]
-    __: u8,
-}
-
-#[repr(C, packed)]
-struct AhciPortHba {
-    command_list_base: u64,
-    fis_base: u64,
-    interrupt_status: AhciPortInterruptStatus,
-    interrupt_enable: AhciPortInterruptEnable,
-    command: AhciPortCommandAndStatus,
-    __: u32,
-    task_file_data: AhciPortTaskFileData,
-    signature: u32,
-    sata_status: AhciSataStatus,
-    sata_control: AhciSataControl,
-    sata_error: AhciSataError,
-    sata_active: u32,
-    command_issue: u32,
-    sata_notification: u32,
-    fis_based_switching_ctl: AhciFisBasedSwitchingControl,
-    device_sleep: AhciDeviceSleep,
-}

rust/sys/denali/src/bin/denali.rs

@@ -25,6 +25,5 @@ extern "C" fn main() -> z_err_t {
     );
 
     mammoth::debug!("AHCI ABAR {:#x}", ahci_controller.pci_header().abar as u64);
-    mammoth::debug!("AHCI Capabilities: {:?}", ahci_controller.ahci_hba());
     0
 }