CMakeLists.txt

@@ -9,7 +9,7 @@ set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_CXX_STANDARD_REQUIRED True)
 set(CMAKE_EXPORT_COMPILE_COMMANDS True)
 
-set(BASE_COMPILE_FLAGS "-ffreestanding -fno-rtti -fno-exceptions -mincoming-stack-boundary=3")
+set(BASE_COMPILE_FLAGS "-ffreestanding -fno-rtti -fno-exceptions")
 set(BASE_LINK_FLAGS "-nostdlib")
 
 add_subdirectory(zion)

lib/mammoth/util/memory_region.h

@@ -25,14 +25,14 @@ class OwnedMemoryRegion {
   static OwnedMemoryRegion ContiguousPhysical(uint64_t size, uint64_t* paddr);
   static OwnedMemoryRegion DirectPhysical(uint64_t paddr, uint64_t size);
 
-  uint64_t vaddr() const { return vaddr_; }
+  uint64_t vaddr() { return vaddr_; }
-  uint64_t size() const { return size_; }
+  uint64_t size() { return size_; }
 
-  z_cap_t cap() const { return vmmo_cap_; }
+  z_cap_t cap() { return vmmo_cap_; }
   z_cap_t DuplicateCap();
 
-  bool empty() const { return vmmo_cap_ == 0; }
+  bool empty() { return vmmo_cap_ != 0; }
-  explicit operator bool() const { return vmmo_cap_ != 0; }
+  explicit operator bool() { return vmmo_cap_ != 0; }
 
  private:
   OwnedMemoryRegion(uint64_t vmmo_cap, uint64_t vaddr, uint64_t size)

sys/denali/CMakeLists.txt

@@ -1,6 +1,7 @@
 add_executable(denali
+  ahci/ahci_device.cpp
   ahci/ahci_controller.cpp
-  ahci/ahci_port.cpp
+  ahci/command.cpp
   denali.cpp
   denali_server.cpp
   )

sys/denali/ahci/ahci.h

@@ -58,13 +58,7 @@ struct AhciHba {
 const uint32_t kCommand_FIS_Receive_Enable = (1 << 4);
 const uint32_t kCommand_Start = 1;
 
-const uint32_t kInterrupt_D2H_FIS = 1;
+struct AhciPort {
-const uint32_t kInterrupt_PIO_FIS = (1 << 1);
-const uint32_t kInterrupt_DMA_FIS = (1 << 2);
-const uint32_t kInterrupt_DeviceBits_FIS = (1 << 3);
-const uint32_t kInterrupt_Unknown_FIS = (1 << 4);
-
-struct AhciPortHba {
   uint64_t command_list_base;
   uint64_t fis_base;
   uint32_t interrupt_status;
@@ -190,9 +184,6 @@ struct PioSetupFis {
   uint8_t rsv4[2];  // Reserved
 } __attribute__((packed));
 
-const uint8_t kIdentifyDevice = 0xEC;
-const uint8_t kDmaReadExt = 0x25;
-
 struct HostToDeviceRegisterFis {
   uint8_t fis_type;  // FIS_TYPE_REG_H2D
   uint8_t pmp_and_c;
@@ -219,7 +210,6 @@ struct HostToDeviceRegisterFis {
   // DWORD 4
   uint32_t reserved;  // Reserved
 } __attribute__((packed));
-
 struct DeviceToHostRegisterFis {
   // DWORD 0
   uint8_t fis_type;  // FIS_TYPE_REG_D2H
@@ -247,13 +237,7 @@ struct DeviceToHostRegisterFis {
 
   uint32_t reserved3;
 } __attribute__((packed));
-
 struct SetDeviceBitsFis {
-  uint8_t fis_type;
-  uint8_t pmport_and_i;
-  uint8_t status;
-  uint8_t error;
-  uint32_t reserved;
 } __attribute__((packed));
 
 struct ReceivedFis {

sys/denali/ahci/ahci_controller.cpp

@@ -28,21 +28,21 @@ glcr::ErrorOr<glcr::UniquePtr<AhciController>> AhciController::Init(
   driver->DumpCapabilities();
   RET_ERR(driver->ResetHba());
   RET_ERR(driver->RegisterIrq());
-  RET_ERR(driver->LoadPorts());
+  RET_ERR(driver->LoadDevices());
   // driver->DumpPorts();
   return driver;
 }
 
-glcr::ErrorOr<AhciPort*> AhciController::GetDevice(uint64_t id) {
+glcr::ErrorOr<AhciDevice*> AhciController::GetDevice(uint64_t id) {
-  if (id >= num_ports_) {
+  if (id >= 32) {
     return glcr::INVALID_ARGUMENT;
   }
 
-  if (ports_[id].empty()) {
+  if (devices_[id].empty()) {
     return glcr::NOT_FOUND;
   }
 
-  return ports_[id].get();
+  return devices_[id].get();
 }
 
 void AhciController::DumpCapabilities() {
@@ -125,13 +125,13 @@ void AhciController::DumpCapabilities() {
 
 void AhciController::DumpPorts() {
   for (uint64_t i = 0; i < 6; i++) {
-    if (ports_[i].empty()) {
+    if (devices_[i].empty()) {
       continue;
     }
 
     dbgln("");
     dbgln("Port {}:", i);
-    ports_[i]->DumpInfo();
+    devices_[i]->DumpInfo();
   }
 }
 
@@ -140,9 +140,10 @@ void AhciController::InterruptLoop() {
   while (true) {
     uint64_t bytes, caps;
     check(ZPortRecv(irq_port_cap_, &bytes, nullptr, &caps, nullptr));
-    for (uint64_t i = 0; i < num_ports_; i++) {
+    for (uint64_t i = 0; i < 32; i++) {
-      if (!ports_[i].empty() && (ahci_hba_->interrupt_status & (1 << i))) {
+      if (!devices_[i].empty() && devices_[i]->IsInit() &&
-        ports_[i]->HandleIrq();
+          (ahci_hba_->interrupt_status & (1 << i))) {
+        devices_[i]->HandleIrq();
         ahci_hba_->interrupt_status &= ~(1 << i);
       }
     }
@@ -229,7 +230,7 @@ glcr::ErrorCode AhciController::ResetHba() {
   return static_cast<glcr::ErrorCode>(ZThreadSleep(50));
 }
 
-glcr::ErrorCode AhciController::LoadPorts() {
+glcr::ErrorCode AhciController::LoadDevices() {
   for (uint8_t i = 0; i <= num_ports_; i++) {
     if (!(ahci_hba_->port_implemented & (1 << i))) {
       continue;
@@ -237,14 +238,13 @@ glcr::ErrorCode AhciController::LoadPorts() {
 
     uint64_t port_addr =
         reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
-    AhciPortHba* port = reinterpret_cast<AhciPortHba*>(port_addr);
+    AhciPort* port = reinterpret_cast<AhciPort*>(port_addr);
     if ((port->sata_status & 0x103) != 0x103) {
       continue;
     }
 
-    ports_[i] = new AhciPort(reinterpret_cast<AhciPortHba*>(port_addr));
+    devices_[i] = new AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
-    // TODO: Maybe continue to the next device if this fails.
+    devices_[i]->DumpInfo();
-    RET_ERR(ports_[i]->Identify());
   }
   return glcr::OK;
 }

sys/denali/ahci/ahci_controller.h

@@ -6,7 +6,7 @@
 #include <ztypes.h>
 
 #include "ahci/ahci.h"
-#include "ahci/ahci_port.h"
+#include "ahci/ahci_device.h"
 
 class AhciController {
  public:
@@ -16,7 +16,7 @@ class AhciController {
 
   void InterruptLoop();
 
-  glcr::ErrorOr<AhciPort*> GetDevice(uint64_t id);
+  glcr::ErrorOr<AhciDevice*> GetDevice(uint64_t id);
 
   void DumpCapabilities();
   void DumpPorts();
@@ -27,7 +27,7 @@ class AhciController {
   mmth::OwnedMemoryRegion ahci_region_;
   volatile AhciHba* ahci_hba_ = nullptr;
 
-  glcr::UniquePtr<AhciPort> ports_[32];
+  glcr::UniquePtr<AhciDevice> devices_[32];
 
   Thread irq_thread_;
   uint64_t irq_port_cap_ = 0;
@@ -38,7 +38,7 @@ class AhciController {
   glcr::ErrorCode LoadCapabilities();
   glcr::ErrorCode LoadHbaRegisters();
   glcr::ErrorCode ResetHba();
-  glcr::ErrorCode LoadPorts();
+  glcr::ErrorCode LoadDevices();
 
   AhciController(mmth::OwnedMemoryRegion&& pci_region)
       : pci_region_(glcr::Move(pci_region)),

sys/denali/ahci/ahci_device.cpp

@@ -0,0 +1,124 @@
+#include "ahci/ahci_device.h"
+
+#include <glacier/status/error.h>
+#include <mammoth/util/debug.h>
+#include <zcall.h>
+
+AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
+  if ((port_struct_->sata_status & 0x103) != 0x103) {
+    crash("Creating device on port without a device",
+          glcr::FAILED_PRECONDITION);
+  }
+
+  // 0x0-0x400 -> Command List
+  // 0x400-0x500 -> Received FIS
+  // 0x500-0x2500 -> Command Tables (0x100 each) (Max PRDT Length is 8 for now)
+  uint64_t paddr;
+  command_structures_ =
+      mmth::OwnedMemoryRegion::ContiguousPhysical(0x2500, &paddr);
+
+  command_list_ = reinterpret_cast<CommandList*>(command_structures_.vaddr());
+  port_struct_->command_list_base = paddr;
+
+  received_fis_ =
+      reinterpret_cast<ReceivedFis*>(command_structures_.vaddr() + 0x400);
+  port_struct_->fis_base = paddr + 0x400;
+  port_struct_->command |= kCommand_FIS_Receive_Enable;
+
+  command_tables_ = glcr::ArrayView(
+      reinterpret_cast<CommandTable*>(command_structures_.vaddr() + 0x500), 32);
+
+  for (uint64_t i = 0; i < 32; i++) {
+    // This leaves space for 2 prdt entries.
+    command_list_->command_headers[i].command_table_base_addr =
+        (paddr + 0x500) + (0x100 * i);
+    commands_[i] = nullptr;
+  }
+  port_struct_->interrupt_enable = 0xFFFFFFFF;
+  port_struct_->sata_error = -1;
+  port_struct_->command |= kCommand_Start;
+}
+
+glcr::ErrorCode AhciDevice::IssueCommand(Command* command) {
+  uint64_t slot;
+  for (slot = 0; slot < 32; slot++) {
+    if (commands_[slot] == nullptr) {
+      break;
+    }
+  }
+  if (slot == 32) {
+    dbgln("All slots full");
+    return glcr::INTERNAL;
+  }
+  command->PopulateFis(command_tables_[slot].command_fis);
+  command->PopulatePrdt(command_tables_[slot].prdt);
+
+  command_list_->command_headers[slot].command =
+      (sizeof(HostToDeviceRegisterFis) / 2) & 0x1F;
+  command_list_->command_headers[slot].prd_table_length = 1;
+  command_list_->command_headers[slot].prd_byte_count = 0;
+
+  commands_[slot] = command;
+
+  commands_issued_ |= (1 << slot);
+  port_struct_->command_issue |= (1 << slot);
+
+  return glcr::OK;
+}
+
+void AhciDevice::DumpInfo() {
+  dbgln("Comlist: {x}", port_struct_->command_list_base);
+  dbgln("FIS: {x}", port_struct_->fis_base);
+  dbgln("Command: {x}", port_struct_->command);
+  dbgln("Signature: {x}", port_struct_->signature);
+  dbgln("SATA status: {x}", port_struct_->sata_status);
+  dbgln("SATA error: {x}", port_struct_->sata_error);
+  dbgln("Int status: {x}", port_struct_->interrupt_status);
+  dbgln("Int enable: {x}", port_struct_->interrupt_enable);
+}
+
+void AhciDevice::HandleIrq() {
+  uint32_t int_status = port_struct_->interrupt_status;
+  // FIXME: Probably only clear the interrupts we know how to handle.
+  port_struct_->interrupt_status = int_status;
+
+  uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
+
+  // FIXME: Pass error codes to the callback.
+  for (uint64_t i = 0; i < 32; i++) {
+    if (commands_finished & (1 << i)) {
+      commands_issued_ &= ~(1 << i);
+      commands_[i]->SignalComplete();
+    }
+  }
+
+  // TODO: Do something with this information.
+  if (int_status & 0x1) {
+    // Device to host.
+    volatile DeviceToHostRegisterFis& fis =
+        received_fis_->device_to_host_register_fis;
+    if (fis.fis_type != FIS_TYPE_REG_D2H) {
+      dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
+            static_cast<uint64_t>(FIS_TYPE_REG_D2H),
+            static_cast<uint64_t>(fis.fis_type));
+      return;
+    }
+    if (fis.error) {
+      dbgln("D2H err: {x}", fis.error);
+      dbgln("status: {x}", fis.status);
+    }
+  }
+  if (int_status & 0x2) {
+    // PIO.
+    volatile PioSetupFis& fis = received_fis_->pio_set_fis;
+    if (fis.fis_type != FIS_TYPE_PIO_SETUP) {
+      dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
+            static_cast<uint64_t>(FIS_TYPE_PIO_SETUP),
+            static_cast<uint64_t>(fis.fis_type));
+      return;
+    }
+    if (fis.error) {
+      dbgln("PIO err: {x}", fis.error);
+    }
+  }
+}

sys/denali/ahci/ahci_device.h

@@ -0,0 +1,38 @@
+#pragma once
+
+#include <glacier/container/array_view.h>
+#include <glacier/status/error.h>
+#include <mammoth/util/memory_region.h>
+#include <ztypes.h>
+
+#include "ahci/ahci.h"
+#include "ahci/command.h"
+
+class AhciDevice {
+ public:
+  AhciDevice() {}
+  // Caller retains ownership of the pointer.
+  AhciDevice(AhciPort* port_struct);
+
+  void DumpInfo();
+
+  bool IsInit() { return port_struct_ != nullptr && command_structures_; }
+
+  glcr::ErrorCode IssueCommand(Command* command);
+
+  void HandleIrq();
+
+  AhciDevice(const AhciDevice&) = delete;
+  AhciDevice& operator=(const AhciDevice&) = delete;
+
+ private:
+  volatile AhciPort* port_struct_ = nullptr;
+  mmth::OwnedMemoryRegion command_structures_;
+
+  volatile CommandList* command_list_ = nullptr;
+  volatile ReceivedFis* received_fis_ = nullptr;
+  glcr::ArrayView<CommandTable> command_tables_;
+
+  Command* commands_[32];
+  uint32_t commands_issued_ = 0;
+};

sys/denali/ahci/ahci_port.cpp

@@ -1,220 +0,0 @@
-#include "ahci/ahci_port.h"
-
-#include <glacier/status/error.h>
-#include <mammoth/util/debug.h>
-#include <zcall.h>
-
-AhciPort::AhciPort(AhciPortHba* port) : port_struct_(port) {
-  if ((port_struct_->sata_status & 0x103) != 0x103) {
-    crash("Creating device on port without a device",
-          glcr::FAILED_PRECONDITION);
-  }
-
-  // 0x0-0x400 -> Command List
-  // 0x400-0x500 -> Received FIS
-  // 0x500-0x2500 -> Command Tables (0x100 each) (Max PRDT Length is 8 for now)
-  uint64_t paddr;
-  command_structures_ =
-      mmth::OwnedMemoryRegion::ContiguousPhysical(0x2500, &paddr);
-
-  command_list_ = reinterpret_cast<CommandList*>(command_structures_.vaddr());
-  port_struct_->command_list_base = paddr;
-
-  received_fis_ =
-      reinterpret_cast<ReceivedFis*>(command_structures_.vaddr() + 0x400);
-  port_struct_->fis_base = paddr + 0x400;
-  port_struct_->command |= kCommand_FIS_Receive_Enable;
-
-  command_tables_ = glcr::ArrayView(
-      reinterpret_cast<CommandTable*>(command_structures_.vaddr() + 0x500), 32);
-
-  commands_issued_ = 0;
-  command_signals_ = glcr::Array<mmth::Semaphore>(32);
-  for (uint64_t i = 0; i < 32; i++) {
-    // This leaves space for 2 prdt entries.
-    command_list_->command_headers[i].command_table_base_addr =
-        (paddr + 0x500) + (0x100 * i);
-  }
-  port_struct_->interrupt_enable = 0xFFFFFFFF;
-  // kInterrupt_D2H_FIS | kInterrupt_PIO_FIS | kInterrupt_DMA_FIS |
-  // kInterrupt_DeviceBits_FIS | kInterrupt_Unknown_FIS;
-  port_struct_->sata_error = -1;
-  port_struct_->command |= kCommand_Start;
-}
-
-glcr::ErrorCode AhciPort::Identify() {
-  if (IsSata()) {
-    CommandInfo identify{
-        .command = kIdentifyDevice,
-        .lba = 0,
-        .sectors = 1,
-        .paddr = 0,
-    };
-    auto region =
-        mmth::OwnedMemoryRegion::ContiguousPhysical(0x200, &identify.paddr);
-    ASSIGN_OR_RETURN(auto* sem, IssueCommand(identify));
-    sem->Wait();
-    uint16_t* ident = reinterpret_cast<uint16_t*>(region.vaddr());
-    uint32_t* sector_size = reinterpret_cast<uint32_t*>(ident + 117);
-    dbgln("Sector size: {}", *sector_size);
-    uint64_t* lbas = reinterpret_cast<uint64_t*>(ident + 100);
-    dbgln("LBA Count: {}", *lbas);
-  }
-  return glcr::OK;
-}
-
-glcr::ErrorOr<mmth::Semaphore*> AhciPort::IssueRead(uint64_t lba,
-                                                    uint16_t sector_cnt,
-                                                    uint64_t paddr) {
-  CommandInfo read{
-      .command = kDmaReadExt,
-      .lba = lba,
-      .sectors = sector_cnt,
-      .paddr = paddr,
-  };
-  return IssueCommand(read);
-}
-
-glcr::ErrorOr<mmth::Semaphore*> AhciPort::IssueCommand(
-    const CommandInfo& command) {
-  uint64_t slot;
-  for (slot = 0; slot < 32; slot++) {
-    if (!(commands_issued_ & (1 << slot))) {
-      break;
-    }
-  }
-  if (slot == 32) {
-    dbgln("All slots full");
-    return glcr::INTERNAL;
-  }
-
-  auto* fis = reinterpret_cast<HostToDeviceRegisterFis*>(
-      command_tables_[slot].command_fis);
-  *fis = HostToDeviceRegisterFis{
-      .fis_type = FIS_TYPE_REG_H2D,
-      .pmp_and_c = 0x80,
-      .command = command.command,
-      .featurel = 0,
-
-      .lba0 = static_cast<uint8_t>(command.lba & 0xFF),
-      .lba1 = static_cast<uint8_t>((command.lba >> 8) & 0xFF),
-      .lba2 = static_cast<uint8_t>((command.lba >> 16) & 0xFF),
-      .device = (1 << 6),  // ATA LBA Mode
-
-      .lba3 = static_cast<uint8_t>((command.lba >> 24) & 0xFF),
-      .lba4 = static_cast<uint8_t>((command.lba >> 32) & 0xFF),
-      .lba5 = static_cast<uint8_t>((command.lba >> 40) & 0xFF),
-      .featureh = 0,
-
-      .count = command.sectors,
-      .icc = 0,
-      .control = 0,
-
-      .reserved = 0,
-  };
-
-  command_tables_[slot].prdt[0].region_address = command.paddr;
-  command_tables_[slot].prdt[0].byte_count = 512 * command.sectors;
-
-  command_list_->command_headers[slot].prd_table_length = 1;
-  command_list_->command_headers[slot].command =
-      (sizeof(HostToDeviceRegisterFis) / 2) & 0x1F;
-  // Set prefetch bit.
-  command_list_->command_headers[slot].command |= (1 << 7);
-
-  // TODO: Synchronization-wise we need to ensure this is set in the same
-  // critical section as where we select a slot.
-  commands_issued_ |= (1 << slot);
-  port_struct_->command_issue |= (1 << slot);
-
-  return &command_signals_[slot];
-}
-
-void AhciPort::DumpInfo() {
-  dbgln("Comlist: {x}", port_struct_->command_list_base);
-  dbgln("FIS: {x}", port_struct_->fis_base);
-  dbgln("Command: {x}", port_struct_->command);
-  dbgln("Signature: {x}", port_struct_->signature);
-  dbgln("SATA status: {x}", port_struct_->sata_status);
-  dbgln("SATA error: {x}", port_struct_->sata_error);
-  dbgln("Int status: {x}", port_struct_->interrupt_status);
-  dbgln("Int enable: {x}", port_struct_->interrupt_enable);
-}
-
-bool CheckFisType(FIS_TYPE expected, uint8_t actual) {
-  if (expected == actual) {
-    return true;
-  }
-  dbgln("BAD FIS TYPE (exp,act): {x}, {x}", static_cast<uint64_t>(expected),
-        static_cast<uint64_t>(actual));
-  return false;
-}
-
-void AhciPort::HandleIrq() {
-  uint32_t int_status = port_struct_->interrupt_status;
-  port_struct_->interrupt_status = int_status;
-
-  bool has_error = false;
-  if (int_status & kInterrupt_D2H_FIS) {
-    dbgln("D2H Received");
-    // Device to host.
-    volatile DeviceToHostRegisterFis& fis =
-        received_fis_->device_to_host_register_fis;
-    if (!CheckFisType(FIS_TYPE_REG_D2H, fis.fis_type)) {
-      return;
-    }
-    if (fis.error) {
-      dbgln("D2H err: {x}", fis.error);
-
-      dbgln("status: {x}", fis.status);
-      dbgln("Error: {x}", port_struct_->sata_error);
-      has_error = true;
-    }
-  }
-  if (int_status & kInterrupt_PIO_FIS) {
-    dbgln("PIO Received");
-    // PIO.
-    volatile PioSetupFis& fis = received_fis_->pio_set_fis;
-    if (!CheckFisType(FIS_TYPE_PIO_SETUP, fis.fis_type)) {
-      return;
-    }
-    dbgln("Count: {x} {x} {x}", fis.counth, fis.countl, fis.e_status);
-    if (fis.error) {
-      dbgln("PIO err: {x}", fis.error);
-      dbgln("status: {x}", fis.status);
-      has_error = true;
-    }
-  }
-  if (int_status & kInterrupt_DMA_FIS) {
-    dbgln("DMA Received");
-    volatile DmaFis& fis = received_fis_->dma_fis;
-    if (!CheckFisType(FIS_TYPE_DMA_SETUP, fis.fis_type)) {
-      return;
-    }
-    // TODO: Actually do something with this FIS.
-  }
-  if (int_status & kInterrupt_DeviceBits_FIS) {
-    dbgln("Device Bits Received");
-    volatile SetDeviceBitsFis& fis = received_fis_->set_device_bits_fis;
-    if (!CheckFisType(FIS_TYPE_DEV_BITS, fis.fis_type)) {
-      return;
-    }
-    if (fis.error) {
-      dbgln("SetDeviceBits err: {x}", fis.error);
-      dbgln("status: {x}", fis.status);
-      has_error = true;
-    }
-  }
-  if (int_status & kInterrupt_Unknown_FIS) {
-    dbgln("Unknown FIS recieved, type: {x}", received_fis_->unknown_fis[0]);
-  }
-  uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
-
-  for (uint64_t i = 0; i < 32; i++) {
-    if (commands_finished & (1 << i)) {
-      // TODO: Pass error codes to the callback.
-      command_signals_[i].Signal();
-      commands_issued_ &= ~(1 << i);
-    }
-  }
-}

sys/denali/ahci/ahci_port.h

@@ -1,47 +0,0 @@
-#pragma once
-
-#include <glacier/container/array.h>
-#include <glacier/container/array_view.h>
-#include <glacier/status/error.h>
-#include <glacier/status/error_or.h>
-#include <mammoth/sync/semaphore.h>
-#include <mammoth/util/memory_region.h>
-#include <ztypes.h>
-
-#include "ahci/ahci.h"
-#include "ahci/command.h"
-
-class AhciPort {
- public:
-  AhciPort() {}
-  // Caller retains ownership of the pointer.
-  AhciPort(AhciPortHba* port_struct);
-
-  void DumpInfo();
-
-  bool IsSata() { return port_struct_->signature == 0x101; }
-  bool IsInit() { return port_struct_ != nullptr && command_structures_; }
-
-  glcr::ErrorCode Identify();
-
-  glcr::ErrorOr<mmth::Semaphore*> IssueRead(uint64_t lba, uint16_t sector_cnt,
-                                            uint64_t paddr);
-
-  void HandleIrq();
-
-  AhciPort(const AhciPort&) = delete;
-  AhciPort& operator=(const AhciPort&) = delete;
-
- private:
-  volatile AhciPortHba* port_struct_ = nullptr;
-  mmth::OwnedMemoryRegion command_structures_;
-
-  volatile CommandList* command_list_ = nullptr;
-  volatile ReceivedFis* received_fis_ = nullptr;
-  glcr::ArrayView<CommandTable> command_tables_;
-
-  glcr::Array<mmth::Semaphore> command_signals_;
-  uint32_t commands_issued_ = 0;
-
-  glcr::ErrorOr<mmth::Semaphore*> IssueCommand(const CommandInfo& command);
-};

sys/denali/ahci/command.cpp

@@ -0,0 +1,63 @@
+#include "ahci/command.h"
+
+#include "ahci/ahci.h"
+
+namespace {
+
+void* memcpy(void* dest, const void* src, uint64_t count) {
+  uint8_t* d = (uint8_t*)dest;
+  const uint8_t* s = (uint8_t*)src;
+  for (uint64_t i = 0; i < count; i++) {
+    d[i] = s[i];
+  }
+  return dest;
+}
+
+}  // namespace
+
+Command::~Command() {}
+
+DmaReadCommand::DmaReadCommand(uint64_t lba, uint64_t sector_cnt,
+                               uint64_t paddr)
+    : lba_(lba),
+      sector_cnt_(sector_cnt),
+      paddr_(paddr),
+      callback_semaphore_() {}
+
+DmaReadCommand::~DmaReadCommand() {}
+
+void DmaReadCommand::PopulateFis(uint8_t* command_fis) {
+  HostToDeviceRegisterFis fis{
+      .fis_type = FIS_TYPE_REG_H2D,
+      .pmp_and_c = 0x80,
+      .command = 0x25,
+      .featurel = 0,
+
+      .lba0 = static_cast<uint8_t>(lba_ & 0xFF),
+      .lba1 = static_cast<uint8_t>((lba_ >> 8) & 0xFF),
+      .lba2 = static_cast<uint8_t>((lba_ >> 16) & 0xFF),
+      .device = (1 << 6),  // ATA LBA Mode
+
+      .lba3 = static_cast<uint8_t>((lba_ >> 24) & 0xFF),
+      .lba4 = static_cast<uint8_t>((lba_ >> 32) & 0xFF),
+      .lba5 = static_cast<uint8_t>((lba_ >> 40) & 0xFF),
+      .featureh = 0,
+
+      .count = static_cast<uint16_t>(sector_cnt_),
+      .icc = 0,
+      .control = 0,
+
+      .reserved = 0,
+  };
+
+  uint64_t bytes = sector_cnt_ * 512;
+
+  memcpy(command_fis, &fis, sizeof(fis));
+}
+void DmaReadCommand::PopulatePrdt(PhysicalRegionDescriptor* prdt) {
+  prdt[0].region_address = paddr_;
+  prdt[0].byte_count = sector_cnt_ * 512;
+}
+
+void DmaReadCommand::SignalComplete() { callback_semaphore_.Signal(); }
+void DmaReadCommand::WaitComplete() { callback_semaphore_.Wait(); }

sys/denali/ahci/command.h

@@ -1,10 +1,36 @@
 #pragma once
 
+#include <mammoth/sync/semaphore.h>
 #include <stdint.h>
 
-struct CommandInfo {
+#include "ahci/ahci.h"
-  uint8_t command;
+
-  uint64_t lba;
+class Command {
-  uint16_t sectors;
+ public:
-  uint64_t paddr;
+  virtual ~Command();
+  virtual void PopulateFis(uint8_t* command_fis) = 0;
+  virtual void PopulatePrdt(PhysicalRegionDescriptor* prdt) = 0;
+  virtual void WaitComplete() = 0;
+  virtual void SignalComplete() = 0;
+};
+
+class DmaReadCommand : public Command {
+ public:
+  DmaReadCommand(uint64_t lba, uint64_t sector_cnt, uint64_t dest_paddr);
+
+  virtual ~DmaReadCommand() override;
+
+  void PopulateFis(uint8_t* command_fis) override;
+  void PopulatePrdt(PhysicalRegionDescriptor* prdt) override;
+
+  void WaitComplete() override;
+  void SignalComplete() override;
+
+ private:
+  uint64_t lba_;
+  uint64_t sector_cnt_;
+  uint64_t paddr_;
+  // TODO: Make this owned by the device so that we don't have to create a new
+  // one with the kernel every time a command is issued.
+  mmth::Semaphore callback_semaphore_;
 };

sys/denali/denali_server.cpp

@@ -14,15 +14,16 @@ glcr::ErrorOr<glcr::UniquePtr<DenaliServer>> DenaliServer::Create(
 
 glcr::Status DenaliServer::HandleRead(const ReadRequest& req,
                                       ReadResponse& resp) {
-  ASSIGN_OR_RETURN(AhciPort * device, driver_.GetDevice(req.device_id()));
+  ASSIGN_OR_RETURN(AhciDevice * device, driver_.GetDevice(req.device_id()));
 
   uint64_t paddr;
   mmth::OwnedMemoryRegion region =
       mmth::OwnedMemoryRegion::ContiguousPhysical(req.size() * 512, &paddr);
 
-  ASSIGN_OR_RETURN(auto semaphore,
+  DmaReadCommand command(req.lba(), req.size(), paddr);
-                   device->IssueRead(req.lba(), req.size(), paddr));
+  device->IssueCommand(&command);
-  semaphore->Wait();
+
+  command.WaitComplete();
 
   resp.set_device_id(req.device_id());
   resp.set_size(req.size());
@@ -32,7 +33,7 @@ glcr::Status DenaliServer::HandleRead(const ReadRequest& req,
 
 glcr::Status DenaliServer::HandleReadMany(const ReadManyRequest& req,
                                           ReadResponse& resp) {
-  ASSIGN_OR_RETURN(AhciPort * device, driver_.GetDevice(req.device_id()));
+  ASSIGN_OR_RETURN(AhciDevice * device, driver_.GetDevice(req.device_id()));
 
   if (req.lba().size() != req.sector_cnt().size()) {
     return glcr::InvalidArgument("LBA and Sector Cnt must be the same length.");
@@ -49,9 +50,9 @@ glcr::Status DenaliServer::HandleReadMany(const ReadManyRequest& req,
   for (uint64_t i = 0; i < req.lba().size(); i++) {
     uint64_t lba = req.lba().at(i);
     uint64_t size = req.sector_cnt().at(i);
-    ASSIGN_OR_RETURN(auto semaphore,
+    DmaReadCommand command(lba, size, region_paddr);
-                     device->IssueRead(lba, size, region_paddr));
+    device->IssueCommand(&command);
-    semaphore->Wait();
+    command.WaitComplete();
 
     region_paddr += size * 512;
   }

zion/interrupt/interrupt.cpp

@@ -113,7 +113,7 @@ extern "C" void interrupt_protection_fault(InterruptFrame* frame) {
   dbgln("RIP: {x}", frame->rip);
   dbgln("RAX: {x}, RBX: {x}, RCX: {x}, RDX: {x}", frame->rax, frame->rbx,
         frame->rcx, frame->rdx);
-  dbgln("RSP: {x}, RBP: {x}", frame->rsp, frame->rbp);
+  dbgln("RSP: {x}", frame->rsp);
   StackUnwind(frame->rbp);
 
   if (IsUserSpace(frame->rip)) {