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No commits in common. "e5da93757ac1182ddbd4341a1786db0f8ec5885a" and "ffa2d97a64caca263f1ebbd213ae30b43ebae3a8" have entirely different histories.
e5da93757a
...
ffa2d97a64
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@ -9,7 +9,7 @@ set(CMAKE_CXX_STANDARD 20)
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set(CMAKE_CXX_STANDARD_REQUIRED True)
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set(CMAKE_CXX_STANDARD_REQUIRED True)
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set(CMAKE_EXPORT_COMPILE_COMMANDS True)
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set(CMAKE_EXPORT_COMPILE_COMMANDS True)
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set(BASE_COMPILE_FLAGS "-fno-rtti -fno-exceptions -mgeneral-regs-only")
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set(BASE_COMPILE_FLAGS "-ffreestanding -fno-exceptions -mgeneral-regs-only")
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set(BASE_LINK_FLAGS "-nostdlib")
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set(BASE_LINK_FLAGS "-nostdlib")
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add_subdirectory(zion)
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add_subdirectory(zion)
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@ -4,5 +4,3 @@
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[[nodiscard]] void* operator new(std::size_t size) { return malloc(size); }
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[[nodiscard]] void* operator new(std::size_t size) { return malloc(size); }
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[[nodiscard]] void* operator new[](std::size_t size) { return malloc(size); }
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[[nodiscard]] void* operator new[](std::size_t size) { return malloc(size); }
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void operator delete(void*, std::size_t) {}
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@ -8,7 +8,6 @@ class Channel {
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Channel() {}
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Channel() {}
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void adopt_cap(uint64_t id);
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void adopt_cap(uint64_t id);
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uint64_t release_cap();
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uint64_t release_cap();
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uint64_t cap();
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z_err_t WriteStr(const char* msg);
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z_err_t WriteStr(const char* msg);
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z_err_t ReadStr(char* buffer, uint64_t* size);
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z_err_t ReadStr(char* buffer, uint64_t* size);
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@ -15,9 +15,6 @@ class MappedMemoryRegion {
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uint64_t paddr() { return paddr_; }
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uint64_t paddr() { return paddr_; }
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uint64_t vaddr() { return vaddr_; }
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uint64_t vaddr() { return vaddr_; }
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uint64_t size() { return size_; }
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uint64_t cap() { return vmmo_cap_; }
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operator bool() { return vmmo_cap_ != 0; }
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operator bool() { return vmmo_cap_ != 0; }
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@ -29,8 +29,6 @@ uint64_t Channel::release_cap() {
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return cap;
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return cap;
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}
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}
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uint64_t Channel::cap() { return chan_cap_; }
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z_err_t Channel::WriteStr(const char* msg) {
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z_err_t Channel::WriteStr(const char* msg) {
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if (!chan_cap_) {
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if (!chan_cap_) {
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return Z_ERR_NULL;
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return Z_ERR_NULL;
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@ -69,7 +69,7 @@ uint64_t LoadElfProgram(uint64_t base, uint64_t as_cap) {
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dbgln("Create mem object");
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dbgln("Create mem object");
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#endif
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#endif
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uint64_t mem_cap;
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uint64_t mem_cap;
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uint64_t size = program.memsz;
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uint64_t size = program.filesz;
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check(ZMemoryObjectCreate(size, &mem_cap));
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check(ZMemoryObjectCreate(size, &mem_cap));
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#if MAM_PROC_DEBUG
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#if MAM_PROC_DEBUG
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@ -1,7 +1,6 @@
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add_executable(denali
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add_executable(denali
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ahci/ahci_device.cpp
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ahci/ahci_device.cpp
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ahci/ahci_driver.cpp
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ahci/ahci_driver.cpp
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ahci/command.cpp
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denali.cpp
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denali.cpp
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denali_server.cpp
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denali_server.cpp
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)
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)
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@ -96,7 +96,7 @@ struct CommandTable {
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uint8_t command_fis[64];
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uint8_t command_fis[64];
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uint8_t atapi_command[16];
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uint8_t atapi_command[16];
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uint8_t reserved[48];
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uint8_t reserved[48];
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PhysicalRegionDescriptor prdt[65535];
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PhysicalRegionDescriptor prds[65535];
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} __attribute__((packed));
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} __attribute__((packed));
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typedef enum {
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typedef enum {
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@ -4,6 +4,12 @@
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#include <string.h>
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#include <string.h>
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#include <zcall.h>
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#include <zcall.h>
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namespace {
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void HandleIdent(AhciDevice* dev) { dev->HandleIdentify(); }
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} // namespace
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AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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if ((port_struct_->sata_status & 0x103) != 0x103) {
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if ((port_struct_->sata_status & 0x103) != 0x103) {
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return;
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return;
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@ -32,25 +38,59 @@ AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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reinterpret_cast<CommandTable*>(command_structures_.vaddr() + ct_off);
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reinterpret_cast<CommandTable*>(command_structures_.vaddr() + ct_off);
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port_struct_->interrupt_enable = 0xFFFFFFFF;
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port_struct_->interrupt_enable = 0xFFFFFFFF;
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if (port_struct_->signature == 0x101) {
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SendIdentify();
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}
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}
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}
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z_err_t AhciDevice::IssueCommand(Command* command) {
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z_err_t AhciDevice::SendIdentify() {
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command->PopulateFis(command_table_->command_fis);
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HostToDeviceRegisterFis fis{
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command->PopulatePrdt(command_table_->prdt);
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.fis_type = FIS_TYPE_REG_H2D,
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.pmp_and_c = 0x80,
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.command = 0xEC,
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.featurel = 0,
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command_list_->command_headers[0].command =
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.lba0 = 0,
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(sizeof(HostToDeviceRegisterFis) / 2) & 0x1F;
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.lba1 = 0,
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.lba2 = 0,
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.device = 0,
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.lba3 = 0,
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.lba4 = 0,
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.lba5 = 0,
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.featureh = 0,
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.count = 0,
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.icc = 0,
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.control = 0,
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.reserved = 0,
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};
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command_list_->command_headers[0].command = (sizeof(fis) / 2) & 0x1F;
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command_list_->command_headers[0].prd_table_length = 1;
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command_list_->command_headers[0].prd_table_length = 1;
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command_list_->command_headers[0].prd_byte_count = 0;
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commands_[0] = command;
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memcpy(command_table_->command_fis, &fis, sizeof(fis));
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commands_[0].region = MappedMemoryRegion::ContiguousPhysical(512);
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// commands_[0].callback = HandleIdent;
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command_table_->prds[0].region_address = commands_[0].region.paddr();
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command_table_->prds[0].byte_count = 512;
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commands_issued_ |= 1;
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port_struct_->command_issue |= 1;
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port_struct_->command_issue |= 1;
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commands_issued_ |= 1;
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return Z_OK;
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return Z_OK;
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}
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}
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void AhciDevice::HandleIdentify() {
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dbgln("Handling Idenify");
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uint16_t* ident = reinterpret_cast<uint16_t*>(commands_[0].region.vaddr());
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dbgln("Ident: %x", ident[0]);
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}
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void AhciDevice::DumpInfo() {
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void AhciDevice::DumpInfo() {
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dbgln("Comlist: %lx", port_struct_->command_list_base);
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dbgln("Comlist: %lx", port_struct_->command_list_base);
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dbgln("FIS: %lx", port_struct_->fis_base);
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dbgln("FIS: %lx", port_struct_->fis_base);
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@ -76,15 +116,11 @@ void AhciDevice::HandleIrq() {
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port_struct_->interrupt_status = int_status;
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port_struct_->interrupt_status = int_status;
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uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
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uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
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dbgln("finished %x", commands_finished);
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dbgln("status %x", int_status);
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dbgln("Issued %x, %x", commands_issued_, port_struct_->command_issue);
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// FIXME: Pass error codes to the callback.
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for (uint64_t i = 0; i < 32; i++) {
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for (uint64_t i = 0; i < 32; i++) {
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if (commands_finished & (1 << i)) {
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if (commands_finished & (1 << i)) {
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// commands_[i].callback(this);
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commands_issued_ &= ~(1 << i);
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commands_issued_ &= ~(1 << i);
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commands_[i]->Callback();
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}
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}
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}
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}
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@ -98,7 +134,6 @@ void AhciDevice::HandleIrq() {
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}
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}
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if (fis.error) {
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if (fis.error) {
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dbgln("D2H err: %x", fis.error);
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dbgln("D2H err: %x", fis.error);
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dbgln("status: %x", fis.status);
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}
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}
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}
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}
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if (int_status & 0x2) {
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if (int_status & 0x2) {
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@ -4,7 +4,6 @@
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#include <zerrors.h>
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#include <zerrors.h>
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#include "ahci/ahci.h"
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#include "ahci/ahci.h"
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#include "ahci/command.h"
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class AhciDevice {
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class AhciDevice {
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public:
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public:
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@ -16,13 +15,11 @@ class AhciDevice {
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bool IsInit() { return port_struct_ != nullptr && command_structures_; }
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bool IsInit() { return port_struct_ != nullptr && command_structures_; }
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z_err_t IssueCommand(Command* command);
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z_err_t SendIdentify();
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void HandleIdentify();
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void HandleIrq();
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void HandleIrq();
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||||||
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|
||||||
AhciDevice(const AhciDevice&) = delete;
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|
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AhciDevice& operator=(const AhciDevice&) = delete;
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|
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private:
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private:
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AhciPort* port_struct_ = nullptr;
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AhciPort* port_struct_ = nullptr;
|
||||||
MappedMemoryRegion command_structures_;
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MappedMemoryRegion command_structures_;
|
||||||
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@ -31,6 +28,10 @@ class AhciDevice {
|
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ReceivedFis* received_fis_ = nullptr;
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ReceivedFis* received_fis_ = nullptr;
|
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CommandTable* command_table_ = nullptr;
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CommandTable* command_table_ = nullptr;
|
||||||
|
|
||||||
Command* commands_[32];
|
struct Command {
|
||||||
volatile uint32_t commands_issued_ = 0;
|
MappedMemoryRegion region;
|
||||||
|
// std::function<void(MappedMemoryRegion)> callback;
|
||||||
|
};
|
||||||
|
Command commands_[32];
|
||||||
|
uint32_t commands_issued_ = 0;
|
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};
|
};
|
||||||
|
|
|
@ -33,16 +33,16 @@ z_err_t AhciDriver::Init() {
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
z_err_t AhciDriver::GetDevice(uint64_t id, AhciDevice** device) {
|
z_err_t AhciDriver::GetDevice(uint64_t id, AhciDevice& device) {
|
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if (id >= 32) {
|
if (id >= 32) {
|
||||||
return Z_ERR_INVALID;
|
return Z_ERR_INVALID;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (devices_[id] != nullptr && !devices_[id]->IsInit()) {
|
if (!devices_[id].IsInit()) {
|
||||||
return Z_ERR_NOT_FOUND;
|
return Z_ERR_NOT_FOUND;
|
||||||
}
|
}
|
||||||
|
|
||||||
*device = devices_[id];
|
device = devices_[id];
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -126,27 +126,24 @@ void AhciDriver::DumpCapabilities() {
|
||||||
|
|
||||||
void AhciDriver::DumpPorts() {
|
void AhciDriver::DumpPorts() {
|
||||||
for (uint64_t i = 0; i < 6; i++) {
|
for (uint64_t i = 0; i < 6; i++) {
|
||||||
AhciDevice* dev = devices_[i];
|
AhciDevice& dev = devices_[i];
|
||||||
if (dev == nullptr || !dev->IsInit()) {
|
if (!dev.IsInit()) {
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
dbgln("");
|
dbgln("");
|
||||||
dbgln("Port %u:", i);
|
dbgln("Port %u:", i);
|
||||||
dev->DumpInfo();
|
dev.DumpInfo();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void AhciDriver::InterruptLoop() {
|
void AhciDriver::InterruptLoop() {
|
||||||
dbgln("Starting interrupt loop");
|
|
||||||
while (true) {
|
while (true) {
|
||||||
uint64_t type, bytes, caps;
|
uint64_t type, bytes, caps;
|
||||||
check(ZPortRecv(irq_port_cap_, 0, 0, 0, 0, &type, &bytes, &caps));
|
check(ZPortRecv(irq_port_cap_, 0, 0, 0, 0, &type, &bytes, &caps));
|
||||||
for (uint64_t i = 0; i < 32; i++) {
|
for (uint64_t i = 0; i < 32; i++) {
|
||||||
if (devices_[i] != nullptr && devices_[i]->IsInit() &&
|
if (devices_[i].IsInit() && (ahci_hba_->interrupt_status & (1 << i))) {
|
||||||
(ahci_hba_->interrupt_status & (1 << i))) {
|
devices_[i].HandleIrq();
|
||||||
dbgln("Interrupt for %u", i);
|
|
||||||
devices_[i]->HandleIrq();
|
|
||||||
ahci_hba_->interrupt_status &= ~(1 << i);
|
ahci_hba_->interrupt_status &= ~(1 << i);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -215,7 +212,7 @@ z_err_t AhciDriver::LoadDevices() {
|
||||||
}
|
}
|
||||||
uint64_t port_addr =
|
uint64_t port_addr =
|
||||||
reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
|
reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
|
||||||
devices_[i] = new AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
|
devices_[i] = AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
|
||||||
}
|
}
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
|
@ -12,7 +12,7 @@ class AhciDriver {
|
||||||
|
|
||||||
void InterruptLoop();
|
void InterruptLoop();
|
||||||
|
|
||||||
z_err_t GetDevice(uint64_t id, AhciDevice** device);
|
z_err_t GetDevice(uint64_t id, AhciDevice& device);
|
||||||
|
|
||||||
void DumpCapabilities();
|
void DumpCapabilities();
|
||||||
void DumpPorts();
|
void DumpPorts();
|
||||||
|
@ -24,7 +24,7 @@ class AhciDriver {
|
||||||
AhciHba* ahci_hba_ = nullptr;
|
AhciHba* ahci_hba_ = nullptr;
|
||||||
|
|
||||||
// TODO: Allocate these dynamically.
|
// TODO: Allocate these dynamically.
|
||||||
AhciDevice* devices_[32];
|
AhciDevice devices_[32];
|
||||||
|
|
||||||
Thread irq_thread_;
|
Thread irq_thread_;
|
||||||
uint64_t irq_port_cap_ = 0;
|
uint64_t irq_port_cap_ = 0;
|
||||||
|
|
|
@ -1,49 +0,0 @@
|
||||||
#include "ahci/command.h"
|
|
||||||
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
#include "ahci/ahci.h"
|
|
||||||
|
|
||||||
Command::~Command() {}
|
|
||||||
|
|
||||||
DmaReadCommand::DmaReadCommand(uint64_t lba, uint64_t sector_cnt,
|
|
||||||
DmaCallback callback)
|
|
||||||
: lba_(lba), sector_cnt_(sector_cnt), callback_(callback) {
|
|
||||||
region_ = MappedMemoryRegion::ContiguousPhysical(sector_cnt * 512);
|
|
||||||
}
|
|
||||||
|
|
||||||
DmaReadCommand::~DmaReadCommand() {}
|
|
||||||
|
|
||||||
void DmaReadCommand::PopulateFis(uint8_t* command_fis) {
|
|
||||||
HostToDeviceRegisterFis fis{
|
|
||||||
.fis_type = FIS_TYPE_REG_H2D,
|
|
||||||
.pmp_and_c = 0x80,
|
|
||||||
.command = 0x25,
|
|
||||||
.featurel = 0,
|
|
||||||
|
|
||||||
.lba0 = static_cast<uint8_t>(lba_ & 0xFF),
|
|
||||||
.lba1 = static_cast<uint8_t>((lba_ >> 8) & 0xFF),
|
|
||||||
.lba2 = static_cast<uint8_t>((lba_ >> 16) & 0xFF),
|
|
||||||
.device = (1 << 6), // ATA LBA Mode
|
|
||||||
|
|
||||||
.lba3 = static_cast<uint8_t>((lba_ >> 24) & 0xFF),
|
|
||||||
.lba4 = static_cast<uint8_t>((lba_ >> 32) & 0xFF),
|
|
||||||
.lba5 = static_cast<uint8_t>((lba_ >> 40) & 0xFF),
|
|
||||||
.featureh = 0,
|
|
||||||
|
|
||||||
.count = static_cast<uint16_t>(sector_cnt_),
|
|
||||||
.icc = 0,
|
|
||||||
.control = 0,
|
|
||||||
|
|
||||||
.reserved = 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
uint64_t bytes = sector_cnt_ * 512;
|
|
||||||
|
|
||||||
memcpy(command_fis, &fis, sizeof(fis));
|
|
||||||
}
|
|
||||||
void DmaReadCommand::PopulatePrdt(PhysicalRegionDescriptor* prdt) {
|
|
||||||
prdt[0].region_address = region_.paddr();
|
|
||||||
prdt[0].byte_count = region_.size();
|
|
||||||
}
|
|
||||||
void DmaReadCommand::Callback() { callback_(lba_, sector_cnt_, region_.cap()); }
|
|
|
@ -1,33 +0,0 @@
|
||||||
#pragma once
|
|
||||||
|
|
||||||
#include <mammoth/memory_region.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
#include "ahci/ahci.h"
|
|
||||||
|
|
||||||
class Command {
|
|
||||||
public:
|
|
||||||
virtual ~Command();
|
|
||||||
virtual void PopulateFis(uint8_t* command_fis) = 0;
|
|
||||||
virtual void PopulatePrdt(PhysicalRegionDescriptor* prdt) = 0;
|
|
||||||
virtual void Callback() = 0;
|
|
||||||
};
|
|
||||||
|
|
||||||
class DmaReadCommand : public Command {
|
|
||||||
public:
|
|
||||||
typedef void (*DmaCallback)(uint64_t, uint64_t, uint64_t);
|
|
||||||
DmaReadCommand(uint64_t lba, uint64_t sector_cnt, DmaCallback callback);
|
|
||||||
|
|
||||||
virtual ~DmaReadCommand() override;
|
|
||||||
|
|
||||||
void PopulateFis(uint8_t* command_fis) override;
|
|
||||||
void PopulatePrdt(PhysicalRegionDescriptor* prdt) override;
|
|
||||||
|
|
||||||
void Callback() override;
|
|
||||||
|
|
||||||
private:
|
|
||||||
uint64_t lba_;
|
|
||||||
uint64_t sector_cnt_;
|
|
||||||
DmaCallback callback_;
|
|
||||||
MappedMemoryRegion region_;
|
|
||||||
};
|
|
|
@ -3,17 +3,8 @@
|
||||||
#include <mammoth/debug.h>
|
#include <mammoth/debug.h>
|
||||||
#include <zcall.h>
|
#include <zcall.h>
|
||||||
|
|
||||||
namespace {
|
|
||||||
DenaliServer* gServer = nullptr;
|
|
||||||
void HandleResponse(uint64_t lba, uint64_t size, uint64_t cap) {
|
|
||||||
gServer->HandleResponse(lba, size, cap);
|
|
||||||
}
|
|
||||||
} // namespace
|
|
||||||
|
|
||||||
DenaliServer::DenaliServer(uint64_t channel_cap, AhciDriver& driver)
|
DenaliServer::DenaliServer(uint64_t channel_cap, AhciDriver& driver)
|
||||||
: channel_cap_(channel_cap), driver_(driver) {
|
: channel_cap_(channel_cap), driver_(driver) {}
|
||||||
gServer = this;
|
|
||||||
}
|
|
||||||
|
|
||||||
z_err_t DenaliServer::RunServer() {
|
z_err_t DenaliServer::RunServer() {
|
||||||
while (true) {
|
while (true) {
|
||||||
|
@ -29,7 +20,12 @@ z_err_t DenaliServer::RunServer() {
|
||||||
case DENALI_READ: {
|
case DENALI_READ: {
|
||||||
DenaliRead* read_req = reinterpret_cast<DenaliRead*>(read_buffer_);
|
DenaliRead* read_req = reinterpret_cast<DenaliRead*>(read_buffer_);
|
||||||
uint64_t memcap = 0;
|
uint64_t memcap = 0;
|
||||||
RET_ERR(HandleRead(*read_req));
|
DenaliReadResponse resp;
|
||||||
|
RET_ERR(HandleRead(*read_req, resp, memcap));
|
||||||
|
uint64_t caps_len = memcap ? 1 : 0;
|
||||||
|
RET_ERR(ZChannelSend(channel_cap_, 0, sizeof(DenaliReadResponse),
|
||||||
|
reinterpret_cast<uint8_t*>(&resp), caps_len,
|
||||||
|
&memcap));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default:
|
default:
|
||||||
|
@ -39,22 +35,10 @@ z_err_t DenaliServer::RunServer() {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
z_err_t DenaliServer::HandleRead(const DenaliRead& read) {
|
z_err_t DenaliServer::HandleRead(const DenaliRead& read,
|
||||||
AhciDevice* device;
|
DenaliReadResponse& resp, uint64_t& memcap) {
|
||||||
RET_ERR(driver_.GetDevice(read.device_id, &device));
|
AhciDevice device;
|
||||||
|
RET_ERR(driver_.GetDevice(read.device_id, device));
|
||||||
device->IssueCommand(
|
|
||||||
new DmaReadCommand(read.lba, read.size, ::HandleResponse));
|
|
||||||
|
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
void DenaliServer::HandleResponse(uint64_t lba, uint64_t size, uint64_t cap) {
|
|
||||||
DenaliReadResponse resp{
|
|
||||||
.device_id = 0,
|
|
||||||
.lba = lba,
|
|
||||||
.size = size,
|
|
||||||
};
|
|
||||||
check(ZChannelSend(channel_cap_, DENALI_READ, sizeof(resp),
|
|
||||||
reinterpret_cast<uint8_t*>(&resp), 1, &cap));
|
|
||||||
}
|
|
||||||
|
|
|
@ -9,8 +9,6 @@ class DenaliServer {
|
||||||
|
|
||||||
z_err_t RunServer();
|
z_err_t RunServer();
|
||||||
|
|
||||||
void HandleResponse(uint64_t lba, uint64_t size, uint64_t cap);
|
|
||||||
|
|
||||||
private:
|
private:
|
||||||
static const uint64_t kBuffSize = 1024;
|
static const uint64_t kBuffSize = 1024;
|
||||||
uint64_t channel_cap_;
|
uint64_t channel_cap_;
|
||||||
|
@ -18,5 +16,6 @@ class DenaliServer {
|
||||||
|
|
||||||
AhciDriver& driver_;
|
AhciDriver& driver_;
|
||||||
|
|
||||||
z_err_t HandleRead(const DenaliRead& read);
|
z_err_t HandleRead(const DenaliRead& read, DenaliReadResponse& resp,
|
||||||
|
uint64_t& mem_cap);
|
||||||
};
|
};
|
||||||
|
|
|
@ -6,34 +6,14 @@
|
||||||
|
|
||||||
#include "hw/pcie.h"
|
#include "hw/pcie.h"
|
||||||
|
|
||||||
int main() {
|
uint64_t main() {
|
||||||
dbgln("Yellowstone Initializing.");
|
dbgln("Yellowstone Initializing.");
|
||||||
uint64_t vaddr;
|
uint64_t vaddr;
|
||||||
check(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, Z_INIT_BOOT_VMMO, &vaddr));
|
check(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, Z_INIT_BOOT_VMMO, &vaddr));
|
||||||
|
|
||||||
Channel local;
|
Channel local;
|
||||||
check(SpawnProcessFromElfRegion(vaddr, local));
|
check(SpawnProcessFromElfRegion(vaddr, local));
|
||||||
|
local.WriteStr("Hello!");
|
||||||
DenaliRead read{
|
|
||||||
.device_id = 0,
|
|
||||||
.lba = 0,
|
|
||||||
.size = 1,
|
|
||||||
};
|
|
||||||
check(ZChannelSend(local.cap(), DENALI_READ, sizeof(DenaliRead),
|
|
||||||
reinterpret_cast<uint8_t*>(&read), 0, nullptr));
|
|
||||||
|
|
||||||
DenaliReadResponse resp;
|
|
||||||
uint64_t mem_cap, type, bytes, caps;
|
|
||||||
|
|
||||||
check(ZChannelRecv(local.cap(), sizeof(resp),
|
|
||||||
reinterpret_cast<uint8_t*>(&resp), 1, &mem_cap, &type,
|
|
||||||
&bytes, &caps));
|
|
||||||
|
|
||||||
dbgln("Resp: %u", type);
|
|
||||||
|
|
||||||
check(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, mem_cap, &vaddr));
|
|
||||||
uint32_t* mbr = reinterpret_cast<uint32_t*>(vaddr + 0x1FE);
|
|
||||||
dbgln("MBR: %x", *mbr);
|
|
||||||
|
|
||||||
DumpPciEDevices();
|
DumpPciEDevices();
|
||||||
|
|
||||||
|
|
|
@ -82,9 +82,7 @@ z_err_t Channel::EnqueueMessage(const ZMessage& msg) {
|
||||||
pending_messages_.PushBack(message);
|
pending_messages_.PushBack(message);
|
||||||
|
|
||||||
if (blocked_threads_.size() > 0) {
|
if (blocked_threads_.size() > 0) {
|
||||||
auto thread = blocked_threads_.PopFront();
|
gScheduler->Enqueue(blocked_threads_.PopFront());
|
||||||
thread->SetState(Thread::RUNNABLE);
|
|
||||||
gScheduler->Enqueue(thread);
|
|
||||||
}
|
}
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
|
@ -27,9 +27,7 @@ z_err_t Port::Write(const ZMessage& msg) {
|
||||||
MutexHolder lock(mutex_);
|
MutexHolder lock(mutex_);
|
||||||
pending_messages_.PushBack(message);
|
pending_messages_.PushBack(message);
|
||||||
if (blocked_threads_.size() > 0) {
|
if (blocked_threads_.size() > 0) {
|
||||||
auto thread = blocked_threads_.PopFront();
|
gScheduler->Enqueue(blocked_threads_.PopFront());
|
||||||
thread->SetState(Thread::RUNNABLE);
|
|
||||||
gScheduler->Enqueue(thread);
|
|
||||||
}
|
}
|
||||||
return Z_OK;
|
return Z_OK;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue