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5 Commits
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5a18d7d559
Author | SHA1 | Date |
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5a18d7d559 | |
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c530921bda | |
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8adde27d9b | |
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66e94ac41b | |
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961389dee8 |
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@ -10,7 +10,9 @@ class ArrayView {
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ArrayView() : data_(nullptr), size_(0) {}
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ArrayView(const ArrayView&) = default;
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ArrayView& operator=(const ArrayView&) = default;
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ArrayView(ArrayView&&) = default;
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ArrayView& operator=(ArrayView&&) = default;
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ArrayView(T* data, uint64_t size) : data_(data), size_(size) {}
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@ -20,6 +20,8 @@ class IntrusiveList {
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void PushFront(const RefPtr<T>& obj);
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void PushBack(const RefPtr<T>& obj);
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void Remove(const RefPtr<T>& obj);
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RefPtr<T> PopFront();
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RefPtr<T> PopBack();
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@ -64,6 +66,29 @@ void IntrusiveList<T>::PushBack(const RefPtr<T>& obj) {
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back_ = obj;
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}
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template <typename T>
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void IntrusiveList<T>::Remove(const RefPtr<T>& obj) {
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if (!obj) {
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return;
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}
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if (front_ == obj) {
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front_ = obj->next_;
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}
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if (back_ == obj) {
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back_ = obj->prev_;
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}
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if (obj->prev_) {
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obj->prev_->next_ = obj->next_;
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}
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if (obj->next_) {
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obj->next_->prev_ = obj->prev_;
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}
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obj->prev_ = nullptr;
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obj->next_ = nullptr;
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size_--;
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}
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template <typename T>
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RefPtr<T> IntrusiveList<T>::PopFront() {
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if (front_ == nullptr) {
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@ -1,6 +1,6 @@
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add_executable(denali
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ahci/ahci_device.cpp
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ahci/ahci_driver.cpp
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ahci/ahci_controller.cpp
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ahci/command.cpp
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denali.cpp
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denali_server.cpp
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@ -37,6 +37,10 @@ struct PciMsiCap {
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uint16_t message_data;
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} __attribute__((packed));
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const uint32_t kGlobalHostControl_HW_Reset = 1;
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const uint32_t kGlobalHostControl_AHCI_Enable = (1 << 31);
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const uint32_t kGlobalHostControl_Interrupt_Enable = (1 << 1);
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struct AhciHba {
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uint32_t capabilities;
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uint32_t global_host_control;
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@ -51,6 +55,9 @@ struct AhciHba {
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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} __attribute__((packed));
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const uint32_t kCommand_FIS_Receive_Enable = (1 << 4);
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const uint32_t kCommand_Start = 1;
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struct AhciPort {
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uint64_t command_list_base;
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uint64_t fis_base;
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@ -1,4 +1,4 @@
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#include "ahci/ahci_driver.h"
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#include "ahci/ahci_controller.h"
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#include <glacier/status/error.h>
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#include <glacier/status/error_or.h>
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@ -11,7 +11,7 @@ namespace {
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const uint64_t kGhc_InteruptEnable = 0x2;
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void interrupt_thread(void* void_driver) {
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AhciDriver* driver = static_cast<AhciDriver*>(void_driver);
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AhciController* driver = static_cast<AhciController*>(void_driver);
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driver->InterruptLoop();
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@ -20,31 +20,32 @@ void interrupt_thread(void* void_driver) {
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} // namespace
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glcr::ErrorOr<glcr::UniquePtr<AhciDriver>> AhciDriver::Init(
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glcr::ErrorOr<glcr::UniquePtr<AhciController>> AhciController::Init(
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mmth::OwnedMemoryRegion&& pci_region) {
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glcr::UniquePtr<AhciDriver> driver(new AhciDriver(glcr::Move(pci_region)));
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// RET_ERR(driver->LoadCapabilities());
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glcr::UniquePtr<AhciController> driver(
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new AhciController(glcr::Move(pci_region)));
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RET_ERR(driver->LoadHbaRegisters());
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RET_ERR(driver->LoadDevices());
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driver->DumpCapabilities();
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RET_ERR(driver->ResetHba());
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RET_ERR(driver->RegisterIrq());
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// driver->DumpCapabilities();
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RET_ERR(driver->LoadDevices());
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// driver->DumpPorts();
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return driver;
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}
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glcr::ErrorOr<AhciDevice*> AhciDriver::GetDevice(uint64_t id) {
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glcr::ErrorOr<AhciDevice*> AhciController::GetDevice(uint64_t id) {
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if (id >= 32) {
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return glcr::INVALID_ARGUMENT;
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}
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if (devices_[id] != nullptr && !devices_[id]->IsInit()) {
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if (devices_[id].empty()) {
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return glcr::NOT_FOUND;
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}
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return devices_[id];
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return devices_[id].get();
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}
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void AhciDriver::DumpCapabilities() {
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void AhciController::DumpCapabilities() {
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dbgln("AHCI Capabilities:");
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uint32_t caps = ahci_hba_->capabilities;
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@ -122,26 +123,25 @@ void AhciDriver::DumpCapabilities() {
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dbgln("Control {x}", ahci_hba_->global_host_control);
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}
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void AhciDriver::DumpPorts() {
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void AhciController::DumpPorts() {
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for (uint64_t i = 0; i < 6; i++) {
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AhciDevice* dev = devices_[i];
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if (dev == nullptr || !dev->IsInit()) {
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if (devices_[i].empty()) {
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continue;
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}
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dbgln("");
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dbgln("Port {}:", i);
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dev->DumpInfo();
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devices_[i]->DumpInfo();
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}
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}
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void AhciDriver::InterruptLoop() {
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void AhciController::InterruptLoop() {
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dbgln("Starting interrupt loop");
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while (true) {
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uint64_t bytes, caps;
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check(ZPortRecv(irq_port_cap_, &bytes, nullptr, &caps, nullptr));
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for (uint64_t i = 0; i < 32; i++) {
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if (devices_[i] != nullptr && devices_[i]->IsInit() &&
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if (!devices_[i].empty() && devices_[i]->IsInit() &&
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(ahci_hba_->interrupt_status & (1 << i))) {
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devices_[i]->HandleIrq();
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ahci_hba_->interrupt_status &= ~(1 << i);
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@ -150,15 +150,17 @@ void AhciDriver::InterruptLoop() {
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}
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}
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glcr::ErrorCode AhciDriver::LoadCapabilities() {
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glcr::ErrorCode AhciController::LoadCapabilities() {
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if (!(pci_device_header_->status_reg & 0x10)) {
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dbgln("No caps!");
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return glcr::FAILED_PRECONDITION;
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}
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uint8_t* base = reinterpret_cast<uint8_t*>(pci_device_header_);
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volatile uint8_t* base =
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reinterpret_cast<volatile uint8_t*>(pci_device_header_);
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uint16_t offset = pci_device_header_->cap_ptr;
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do {
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uint16_t* cap = reinterpret_cast<uint16_t*>(base + offset);
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volatile uint16_t* cap =
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reinterpret_cast<volatile uint16_t*>(base + offset);
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switch (*cap & 0xFF) {
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case 0x01:
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dbgln("Power Management");
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@ -179,7 +181,7 @@ glcr::ErrorCode AhciDriver::LoadCapabilities() {
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::RegisterIrq() {
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glcr::ErrorCode AhciController::RegisterIrq() {
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if (pci_device_header_->interrupt_pin == 0) {
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crash("Can't register IRQ without a pin num", glcr::INVALID_ARGUMENT);
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}
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@ -205,7 +207,7 @@ glcr::ErrorCode AhciDriver::RegisterIrq() {
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::LoadHbaRegisters() {
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glcr::ErrorCode AhciController::LoadHbaRegisters() {
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ahci_region_ = mmth::OwnedMemoryRegion ::DirectPhysical(
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pci_device_header_->abar, 0x1100);
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ahci_hba_ = reinterpret_cast<AhciHba*>(ahci_region_.vaddr());
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@ -215,15 +217,34 @@ glcr::ErrorCode AhciDriver::LoadHbaRegisters() {
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::LoadDevices() {
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for (uint8_t i = 0; i < 32; i++) {
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glcr::ErrorCode AhciController::ResetHba() {
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ahci_hba_->global_host_control |= kGlobalHostControl_HW_Reset;
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// TODO: Consider sleeping here.
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while (ahci_hba_->global_host_control & kGlobalHostControl_HW_Reset) {
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continue;
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}
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ahci_hba_->global_host_control |= kGlobalHostControl_AHCI_Enable;
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return static_cast<glcr::ErrorCode>(ZThreadSleep(50));
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}
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glcr::ErrorCode AhciController::LoadDevices() {
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for (uint8_t i = 0; i <= num_ports_; i++) {
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if (!(ahci_hba_->port_implemented & (1 << i))) {
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devices_[i] = nullptr;
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
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AhciPort* port = reinterpret_cast<AhciPort*>(port_addr);
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if ((port->sata_status & 0x103) != 0x103) {
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continue;
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}
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devices_[i] = new AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
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devices_[i]->DumpInfo();
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}
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return glcr::OK;
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}
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@ -8,9 +8,9 @@
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#include "ahci/ahci.h"
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#include "ahci/ahci_device.h"
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class AhciDriver {
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class AhciController {
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public:
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static glcr::ErrorOr<glcr::UniquePtr<AhciDriver>> Init(
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static glcr::ErrorOr<glcr::UniquePtr<AhciController>> Init(
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mmth::OwnedMemoryRegion&& ahci_phys);
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glcr::ErrorCode RegisterIrq();
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@ -23,24 +23,24 @@ class AhciDriver {
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private:
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mmth::OwnedMemoryRegion pci_region_;
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PciDeviceHeader* pci_device_header_ = nullptr;
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volatile PciDeviceHeader* pci_device_header_ = nullptr;
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mmth::OwnedMemoryRegion ahci_region_;
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AhciHba* ahci_hba_ = nullptr;
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volatile AhciHba* ahci_hba_ = nullptr;
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// TODO: Allocate these dynamically.
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AhciDevice* devices_[32];
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glcr::UniquePtr<AhciDevice> devices_[32];
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Thread irq_thread_;
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uint64_t irq_port_cap_ = 0;
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uint64_t num_ports_;
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uint64_t num_commands_;
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uint8_t num_ports_;
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uint8_t num_commands_;
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glcr::ErrorCode LoadCapabilities();
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glcr::ErrorCode LoadHbaRegisters();
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glcr::ErrorCode ResetHba();
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glcr::ErrorCode LoadDevices();
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AhciDriver(mmth::OwnedMemoryRegion&& pci_region)
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AhciController(mmth::OwnedMemoryRegion&& pci_region)
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: pci_region_(glcr::Move(pci_region)),
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pci_device_header_(
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reinterpret_cast<PciDeviceHeader*>(pci_region_.vaddr())) {}
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@ -6,7 +6,8 @@
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AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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if ((port_struct_->sata_status & 0x103) != 0x103) {
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return;
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crash("Creating device on port without a device",
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glcr::FAILED_PRECONDITION);
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}
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// 0x0-0x400 -> Command List
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@ -22,35 +23,45 @@ AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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received_fis_ =
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reinterpret_cast<ReceivedFis*>(command_structures_.vaddr() + 0x400);
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port_struct_->fis_base = paddr + 0x400;
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port_struct_->command |= kCommand_FIS_Receive_Enable;
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command_tables_ =
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reinterpret_cast<CommandTable*>(command_structures_.vaddr() + 0x500);
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command_tables_ = glcr::ArrayView(
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reinterpret_cast<CommandTable*>(command_structures_.vaddr() + 0x500), 32);
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for (uint64_t i = 0; i < 32; i++) {
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// This leaves space for 2 prdt entries.
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command_list_->command_headers[i].command_table_base_addr =
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(paddr + 0x500) + (0x100 * i);
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commands_[i] = nullptr;
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}
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port_struct_->interrupt_enable = 0xFFFFFFFF;
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// Reset the CMD and FRE bits since we move these structures.
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// FIXME: I think we need to poll these bits to make sure they become
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// 0 before setting them back to one.
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port_struct_->command &= ~(0x00000011);
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port_struct_->command |= 0x00000011;
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port_struct_->sata_error = -1;
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port_struct_->command |= kCommand_Start;
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}
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glcr::ErrorCode AhciDevice::IssueCommand(Command* command) {
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command->PopulateFis(command_tables_->command_fis);
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command->PopulatePrdt(command_tables_->prdt);
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uint64_t slot;
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for (slot = 0; slot < 32; slot++) {
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if (commands_[slot] == nullptr) {
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break;
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}
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}
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if (slot == 32) {
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dbgln("All slots full");
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return glcr::INTERNAL;
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}
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command->PopulateFis(command_tables_[slot].command_fis);
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command->PopulatePrdt(command_tables_[slot].prdt);
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command_list_->command_headers[0].command =
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command_list_->command_headers[slot].command =
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(sizeof(HostToDeviceRegisterFis) / 2) & 0x1F;
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command_list_->command_headers[0].prd_table_length = 1;
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command_list_->command_headers[0].prd_byte_count = 0;
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command_list_->command_headers[slot].prd_table_length = 1;
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command_list_->command_headers[slot].prd_byte_count = 0;
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commands_[0] = command;
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commands_[slot] = command;
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commands_issued_ |= 1;
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port_struct_->command_issue |= 1;
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commands_issued_ |= (1 << slot);
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port_struct_->command_issue |= (1 << slot);
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return glcr::OK;
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}
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|
@ -61,17 +72,9 @@ void AhciDevice::DumpInfo() {
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dbgln("Command: {x}", port_struct_->command);
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dbgln("Signature: {x}", port_struct_->signature);
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dbgln("SATA status: {x}", port_struct_->sata_status);
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dbgln("SATA error: {x}", port_struct_->sata_error);
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dbgln("Int status: {x}", port_struct_->interrupt_status);
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dbgln("Int enable: {x}", port_struct_->interrupt_enable);
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|
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// Just dump one command info for now.
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for (uint64_t i = 0; i < 32; i++) {
|
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dbgln("Command Header: {}", i);
|
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dbgln("Command {x}", command_list_->command_headers[i].command);
|
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dbgln("PRD Len: {x}", command_list_->command_headers[i].prd_table_length);
|
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dbgln("Command Table {x}",
|
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command_list_->command_headers[i].command_table_base_addr);
|
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}
|
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}
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|
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void AhciDevice::HandleIrq() {
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|
@ -92,7 +95,8 @@ void AhciDevice::HandleIrq() {
|
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// TODO: Do something with this information.
|
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if (int_status & 0x1) {
|
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// Device to host.
|
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DeviceToHostRegisterFis& fis = received_fis_->device_to_host_register_fis;
|
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volatile DeviceToHostRegisterFis& fis =
|
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received_fis_->device_to_host_register_fis;
|
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if (fis.fis_type != FIS_TYPE_REG_D2H) {
|
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dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
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static_cast<uint64_t>(FIS_TYPE_REG_D2H),
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|
@ -106,7 +110,7 @@ void AhciDevice::HandleIrq() {
|
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}
|
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if (int_status & 0x2) {
|
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// PIO.
|
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PioSetupFis& fis = received_fis_->pio_set_fis;
|
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volatile PioSetupFis& fis = received_fis_->pio_set_fis;
|
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if (fis.fis_type != FIS_TYPE_PIO_SETUP) {
|
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dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
|
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static_cast<uint64_t>(FIS_TYPE_PIO_SETUP),
|
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|
|
|
@ -1,5 +1,6 @@
|
|||
#pragma once
|
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|
||||
#include <glacier/container/array_view.h>
|
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#include <glacier/status/error.h>
|
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#include <mammoth/util/memory_region.h>
|
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#include <ztypes.h>
|
||||
|
@ -25,13 +26,13 @@ class AhciDevice {
|
|||
AhciDevice& operator=(const AhciDevice&) = delete;
|
||||
|
||||
private:
|
||||
AhciPort* port_struct_ = nullptr;
|
||||
volatile AhciPort* port_struct_ = nullptr;
|
||||
mmth::OwnedMemoryRegion command_structures_;
|
||||
|
||||
CommandList* command_list_ = nullptr;
|
||||
ReceivedFis* received_fis_ = nullptr;
|
||||
CommandTable* command_tables_ = nullptr;
|
||||
volatile CommandList* command_list_ = nullptr;
|
||||
volatile ReceivedFis* received_fis_ = nullptr;
|
||||
glcr::ArrayView<CommandTable> command_tables_;
|
||||
|
||||
Command* commands_[32];
|
||||
volatile uint32_t commands_issued_ = 0;
|
||||
uint32_t commands_issued_ = 0;
|
||||
};
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
#include <stdint.h>
|
||||
#include <yellowstone/yellowstone.yunq.client.h>
|
||||
|
||||
#include "ahci/ahci_driver.h"
|
||||
#include "ahci/ahci_controller.h"
|
||||
#include "denali_server.h"
|
||||
|
||||
using yellowstone::AhciInfo;
|
||||
|
@ -19,7 +19,7 @@ uint64_t main(uint64_t init_port_cap) {
|
|||
check(stub.GetAhciInfo(ahci));
|
||||
mmth::OwnedMemoryRegion ahci_region =
|
||||
mmth::OwnedMemoryRegion::FromCapability(ahci.ahci_region());
|
||||
ASSIGN_OR_RETURN(auto driver, AhciDriver::Init(glcr::Move(ahci_region)));
|
||||
ASSIGN_OR_RETURN(auto driver, AhciController::Init(glcr::Move(ahci_region)));
|
||||
|
||||
ASSIGN_OR_RETURN(glcr::UniquePtr<DenaliServer> server,
|
||||
DenaliServer::Create(*driver));
|
||||
|
|
|
@ -6,7 +6,7 @@
|
|||
#include <zcall.h>
|
||||
|
||||
glcr::ErrorOr<glcr::UniquePtr<DenaliServer>> DenaliServer::Create(
|
||||
AhciDriver& driver) {
|
||||
AhciController& driver) {
|
||||
z_cap_t cap;
|
||||
RET_ERR(ZEndpointCreate(&cap));
|
||||
return glcr::UniquePtr<DenaliServer>(new DenaliServer(cap, driver));
|
||||
|
|
|
@ -2,13 +2,13 @@
|
|||
|
||||
#include <glacier/status/error.h>
|
||||
|
||||
#include "ahci/ahci_driver.h"
|
||||
#include "ahci/ahci_controller.h"
|
||||
#include "lib/denali/denali.yunq.server.h"
|
||||
|
||||
class DenaliServer : public DenaliServerBase {
|
||||
public:
|
||||
static glcr::ErrorOr<glcr::UniquePtr<DenaliServer>> Create(
|
||||
AhciDriver& driver);
|
||||
AhciController& driver);
|
||||
|
||||
glcr::Status HandleRead(const ReadRequest& req, ReadResponse& resp) override;
|
||||
glcr::Status HandleReadMany(const ReadManyRequest& req,
|
||||
|
@ -18,8 +18,8 @@ class DenaliServer : public DenaliServerBase {
|
|||
static const uint64_t kBuffSize = 1024;
|
||||
uint8_t read_buffer_[kBuffSize];
|
||||
|
||||
AhciDriver& driver_;
|
||||
AhciController& driver_;
|
||||
|
||||
DenaliServer(z_cap_t endpoint_cap, AhciDriver& driver)
|
||||
DenaliServer(z_cap_t endpoint_cap, AhciController& driver)
|
||||
: DenaliServerBase(endpoint_cap), driver_(driver) {}
|
||||
};
|
||||
|
|
|
@ -68,9 +68,14 @@ void Terminal::ExecuteCommand(const glcr::String& command) {
|
|||
}
|
||||
auto file = mmth::File::Open(tokens[1]);
|
||||
|
||||
// TODO: Wait until the process exits.
|
||||
auto error_or_cap = mmth::SpawnProcessFromElfRegion(
|
||||
(uint64_t)file.raw_ptr(), gInitEndpointCap);
|
||||
z_cap_t endpoint;
|
||||
if (ZCapDuplicate(gInitEndpointCap, kZionPerm_All, &endpoint) != glcr::OK) {
|
||||
console_.WriteString("Couldn't duplicate yellowstone cap for spawn");
|
||||
return;
|
||||
}
|
||||
|
||||
auto error_or_cap =
|
||||
mmth::SpawnProcessFromElfRegion((uint64_t)file.raw_ptr(), endpoint);
|
||||
if (!error_or_cap.ok()) {
|
||||
console_.WriteString(
|
||||
glcr::StrFormat("Error: {}\n", error_or_cap.error()));
|
||||
|
|
|
@ -1,7 +1,10 @@
|
|||
#include <mammoth/util/debug.h>
|
||||
#include <zcall.h>
|
||||
|
||||
uint64_t main(uint64_t init_port_cap) {
|
||||
dbgln("testbed");
|
||||
check(ZThreadSleep(2000));
|
||||
dbgln("testbed2");
|
||||
|
||||
return glcr::OK;
|
||||
}
|
||||
|
|
|
@ -17,6 +17,7 @@ SYS4(ThreadStart, z_cap_t, thread_cap, uint64_t, entry, uint64_t, arg1,
|
|||
uint64_t, arg2);
|
||||
SYS0(ThreadExit);
|
||||
SYS1(ThreadWait, z_cap_t, thread_cap);
|
||||
SYS1(ThreadSleep, uint64_t, millis);
|
||||
|
||||
SYS5(AddressSpaceMap, z_cap_t, vmas_cap, uint64_t, vmas_offset, z_cap_t,
|
||||
vmmo_cap, uint64_t, align, uint64_t*, vaddr);
|
||||
|
|
|
@ -19,6 +19,7 @@ const uint64_t kZionThreadCreate = 0x10;
|
|||
const uint64_t kZionThreadStart = 0x11;
|
||||
const uint64_t kZionThreadExit = 0x12;
|
||||
const uint64_t kZionThreadWait = 0x13;
|
||||
const uint64_t kZionThreadSleep = 0x14;
|
||||
|
||||
// Memory Calls
|
||||
const uint64_t kZionAddressSpaceMap = 0x21;
|
||||
|
|
|
@ -29,6 +29,7 @@ class Thread : public KernelObject, public glcr::IntrusiveListNode<Thread> {
|
|||
RUNNING,
|
||||
RUNNABLE,
|
||||
BLOCKED,
|
||||
SLEEPING,
|
||||
CLEANUP,
|
||||
FINISHED,
|
||||
};
|
||||
|
@ -69,6 +70,9 @@ class Thread : public KernelObject, public glcr::IntrusiveListNode<Thread> {
|
|||
|
||||
void Wait();
|
||||
|
||||
void SetSleepTicks(uint64_t sleep_ticks) { sleep_ticks_ = sleep_ticks; }
|
||||
bool DecrementSleepTicks() { return --sleep_ticks_ == 0; }
|
||||
|
||||
private:
|
||||
friend class glcr::MakeRefCountedFriend<Thread>;
|
||||
Thread(Process& proc, uint64_t tid);
|
||||
|
@ -79,6 +83,7 @@ class Thread : public KernelObject, public glcr::IntrusiveListNode<Thread> {
|
|||
State state_ = CREATED;
|
||||
bool is_kernel_ = false;
|
||||
uint64_t user_stack_base_;
|
||||
uint64_t sleep_ticks_;
|
||||
|
||||
// Startup Context for the thread.
|
||||
uint64_t rip_;
|
||||
|
|
|
@ -45,14 +45,11 @@ void Scheduler::Preempt() {
|
|||
return;
|
||||
}
|
||||
|
||||
DecrementSleepingThreads();
|
||||
|
||||
ClearDeadThreadsFromFront();
|
||||
|
||||
asm volatile("cli");
|
||||
if (current_thread_ == sleep_thread_) {
|
||||
// Sleep should never be preempted. (We should yield it if another thread
|
||||
// becomes scheduleable).
|
||||
return;
|
||||
}
|
||||
|
||||
if (runnable_threads_.size() == 0) {
|
||||
// Continue.
|
||||
|
@ -102,9 +99,33 @@ void Scheduler::Yield() {
|
|||
SwapToCurrent(*prev);
|
||||
}
|
||||
|
||||
void Scheduler::Sleep(uint64_t millis) {
|
||||
// FIXME: Improve resolution of sleep calls.
|
||||
uint64_t ticks = (millis / 50) + 1;
|
||||
current_thread_->SetSleepTicks(ticks);
|
||||
current_thread_->SetState(Thread::SLEEPING);
|
||||
sleeping_threads_.PushBack(current_thread_);
|
||||
Yield();
|
||||
}
|
||||
|
||||
void Scheduler::ClearDeadThreadsFromFront() {
|
||||
while (runnable_threads_.size() > 0 &&
|
||||
runnable_threads_.PeekFront()->IsDying()) {
|
||||
runnable_threads_.PopFront();
|
||||
}
|
||||
}
|
||||
|
||||
void Scheduler::DecrementSleepingThreads() {
|
||||
auto thread = sleeping_threads_.PeekFront();
|
||||
while (thread) {
|
||||
if (thread->DecrementSleepTicks()) {
|
||||
auto thread_next = thread->next_;
|
||||
sleeping_threads_.Remove(thread);
|
||||
thread->SetState(Thread::RUNNABLE);
|
||||
runnable_threads_.PushBack(thread);
|
||||
thread = thread_next;
|
||||
} else {
|
||||
thread = thread->next_;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -23,18 +23,23 @@ class Scheduler {
|
|||
void Preempt();
|
||||
void Yield();
|
||||
|
||||
void Sleep(uint64_t millis);
|
||||
|
||||
private:
|
||||
bool enabled_ = false;
|
||||
|
||||
glcr::RefPtr<Thread> current_thread_;
|
||||
glcr::IntrusiveList<Thread> runnable_threads_;
|
||||
|
||||
glcr::IntrusiveList<Thread> sleeping_threads_;
|
||||
|
||||
glcr::RefPtr<Thread> sleep_thread_;
|
||||
|
||||
Scheduler();
|
||||
void SwapToCurrent(Thread& prev);
|
||||
|
||||
void ClearDeadThreadsFromFront();
|
||||
void DecrementSleepingThreads();
|
||||
};
|
||||
|
||||
extern Scheduler* gScheduler;
|
||||
|
|
|
@ -59,6 +59,7 @@ extern "C" z_err_t SyscallHandler(uint64_t call_id, void* req) {
|
|||
CASE(ThreadStart);
|
||||
CASE(ThreadExit);
|
||||
CASE(ThreadWait);
|
||||
CASE(ThreadSleep);
|
||||
// syscall/address_space.h
|
||||
CASE(AddressSpaceMap);
|
||||
CASE(AddressSpaceUnmap);
|
||||
|
|
|
@ -53,3 +53,8 @@ glcr::ErrorCode ThreadWait(ZThreadWaitReq* req) {
|
|||
thread->Wait();
|
||||
return glcr::OK;
|
||||
}
|
||||
|
||||
glcr::ErrorCode ThreadSleep(ZThreadSleepReq* req) {
|
||||
gScheduler->Sleep(req->millis);
|
||||
return glcr::OK;
|
||||
}
|
||||
|
|
|
@ -8,3 +8,4 @@ glcr::ErrorCode ThreadCreate(ZThreadCreateReq* req);
|
|||
glcr::ErrorCode ThreadStart(ZThreadStartReq* req);
|
||||
glcr::ErrorCode ThreadExit(ZThreadExitReq*);
|
||||
glcr::ErrorCode ThreadWait(ZThreadWaitReq* req);
|
||||
glcr::ErrorCode ThreadSleep(ZThreadSleepReq* req);
|
||||
|
|
Loading…
Reference in New Issue