85 lines
2.2 KiB
C++
85 lines
2.2 KiB
C++
#include "xhci/trb.h"
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constexpr uint8_t kTrb_TypeOffset = 10;
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constexpr uint16_t kTrb_Cycle = 1;
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constexpr uint16_t kTrb_ToggleCycle = (1 << 1);
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constexpr uint16_t kTrb_InterruptShortPacket = (1 << 2);
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constexpr uint16_t kTrb_Interrupt = (1 << 5);
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constexpr uint16_t kTrb_BSR = (1 << 9);
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namespace {
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uint16_t TypeToInt(TrbType type) {
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return static_cast<uint16_t>(type) << kTrb_TypeOffset;
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}
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} // namespace
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TrbType GetType(const XhciTrb& trb) {
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return TrbType(trb.type_and_cycle >> kTrb_TypeOffset);
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}
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XhciTrb CreateNormalTrb(uint64_t physical_address, uint8_t size) {
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return {
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.parameter = physical_address,
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.status = size,
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.type_and_cycle = (uint16_t)(TypeToInt(TrbType::Normal) | kTrb_Cycle |
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kTrb_Interrupt | kTrb_InterruptShortPacket),
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.control = 0,
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};
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}
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XhciTrb CreateLinkTrb(uint64_t physical_address) {
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return {
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.parameter = physical_address,
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.status = 0,
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.type_and_cycle = (uint16_t)(TypeToInt(TrbType::Link) | kTrb_ToggleCycle),
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.control = 0,
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};
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}
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XhciTrb CreateEnableSlotTrb() {
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return {
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.parameter = 0,
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.status = 0,
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// FIXME: Accept Cycle Bit as a parameter.
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.type_and_cycle = (uint16_t)(TypeToInt(TrbType::EnableSlot) | kTrb_Cycle),
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// FIXME: Specify slot type if necessary. (XHCI Table 7-9)?
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.control = 0,
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};
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}
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XhciTrb CreateAddressDeviceCommand(uint64_t input_context, uint8_t slot_id) {
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return {
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.parameter = input_context,
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.status = 0,
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// Always cycle the device straight to addressed.
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.type_and_cycle =
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(uint16_t)(TypeToInt(TrbType::AddressDevice) | kTrb_Cycle),
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.control = (uint16_t)(slot_id << 8),
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};
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}
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XhciTrb CreateConfigureEndpointCommand(uint64_t input_context,
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uint8_t slot_id) {
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return {
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.parameter = input_context,
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.status = 0,
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.type_and_cycle =
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(uint16_t)(TypeToInt(TrbType::ConfigureEndpoint) | kTrb_Cycle),
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.control = (uint16_t)(slot_id << 8),
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};
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}
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XhciTrb CreateNoOpCommandTrb() {
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return {
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.parameter = 0,
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.status = 0,
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// FIXME: Accept Cycle Bit as a parameter.
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.type_and_cycle =
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(uint16_t)(TypeToInt(TrbType::NoOpCommand) | kTrb_Cycle),
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.control = 0,
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};
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}
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