404 lines
9.2 KiB
Rust
404 lines
9.2 KiB
Rust
use bitfield_struct::bitfield;
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#[bitfield(u32)]
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pub struct AhciPortInterruptStatus {
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pub device_to_host_register_fis_interrupt: bool,
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pub pio_setup_fis_interrupt: bool,
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pub dma_setup_fis_interrupt: bool,
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pub set_device_bits_interrupt: bool,
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#[bits(access = RO)]
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pub unknown_fis_interrupt: bool,
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pub descriptor_prossed: bool,
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#[bits(access = RO)]
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pub port_connect_change_status: bool,
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pub device_mechanical_presence_status: bool,
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#[bits(14)]
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__: u32,
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#[bits(access = RO)]
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pub phy_rdy_change_status: bool,
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pub incorrect_port_multiplier_status: bool,
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pub overflow_status: bool,
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__: bool,
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pub interface_non_fatal_error_status: bool,
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pub interface_fatal_error_status: bool,
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pub host_bus_data_error_status: bool,
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pub host_bus_fatal_error_status: bool,
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pub task_file_error_status: bool,
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pub cold_port_detect_status: bool,
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}
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#[bitfield(u32)]
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pub struct AhciPortInterruptEnable {
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pub device_to_host_register_fis_enable: bool,
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pub pio_setup_fis_enable: bool,
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pub dma_setup_fis_enable: bool,
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pub set_device_bits_fis_enable: bool,
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pub unknown_fis_enable: bool,
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pub descriptor_processed_enable: bool,
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pub port_change_enable: bool,
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pub device_mechanical_presence_enable: bool,
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#[bits(14)]
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__: u32,
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pub phy_rdy_change_enable: bool,
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pub incorrect_port_multiplier_enable: bool,
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pub overflow_enable: bool,
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__: bool,
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pub interface_non_fatal_error_enable: bool,
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pub interface_fatal_error_enable: bool,
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pub host_bus_data_error_enable: bool,
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pub host_bust_fatal_error_enable: bool,
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pub task_file_error_enable: bool,
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pub cold_presence_detect_enable: bool,
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}
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#[repr(u8)]
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#[derive(Debug)]
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enum InterfaceCommunicationControl {
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NoOpOrIdle = 0x0,
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Active = 0x1,
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Partial = 0x2,
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Slumber = 0x6,
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DevSleep = 0x8,
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Unknown = 0xF,
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}
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impl InterfaceCommunicationControl {
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoOpOrIdle,
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0x1 => Self::Active,
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0x2 => Self::Partial,
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0x6 => Self::Slumber,
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0x8 => Self::DevSleep,
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_ => Self::Unknown,
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}
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}
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const fn into_bits(self) -> u8 {
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self as _
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}
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}
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#[bitfield(u32)]
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pub struct AhciPortCommandAndStatus {
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pub start: bool,
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pub spin_up_device: bool,
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pub power_on_device: bool,
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pub command_list_overide: bool,
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pub fis_recieve_enable: bool,
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#[bits(3)]
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__: u8,
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#[bits(5, access = RO)]
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pub current_command_slot: u8,
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#[bits(access = RO)]
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pub mechanical_presence_switch_state: bool,
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#[bits(access = RO)]
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pub fis_receive_running: bool,
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#[bits(access = RO)]
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pub command_list_running: bool,
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#[bits(access = RO)]
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pub cold_presence_state: bool,
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pub port_multipler_attached: bool,
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#[bits(access = RO)]
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pub hot_plug_capable_port: bool,
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#[bits(access = RO)]
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pub mechanical_presence_switch_attached_to_port: bool,
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#[bits(access = RO)]
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pub cold_presence_detection: bool,
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#[bits(access = RO)]
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pub external_sata_port: bool,
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#[bits(access = RO)]
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pub fis_base_switch_capable: bool,
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pub automatic_partial_to_slumber_transitions_enable: bool,
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pub device_is_atapi: bool,
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pub drive_led_on_atapi_enable: bool,
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pub aggressive_power_link_management_enable: bool,
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pub aggressive_slumber_partial: bool,
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#[bits(4)]
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pub interface_communication_control: InterfaceCommunicationControl,
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}
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#[bitfield(u32)]
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pub struct AhciPortTaskFileData {
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#[bits(access = RO)]
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err_status: bool,
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#[bits(2, access = RO)]
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command_specific_status_lo: u8,
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#[bits(access = RO)]
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data_transfer_requested: bool,
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#[bits(3, access = RO)]
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command_specific_status_hi: u8,
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#[bits(access = RO)]
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busy_status: bool,
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#[bits(8, access = RO)]
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error: u8,
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#[bits(16)]
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__: u16,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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pub enum AhciDeviceDetection {
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NoDevice = 0x0,
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NoCommunication = 0x1,
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CommunicationEstablished = 0x3,
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OfflineMode = 0x4,
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Unknown = 0xF,
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}
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impl AhciDeviceDetection {
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoDevice,
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0x1 => Self::NoCommunication,
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0x3 => Self::CommunicationEstablished,
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0x4 => Self::OfflineMode,
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_ => Self::Unknown,
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}
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}
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}
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#[derive(Copy, Clone, Debug)]
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#[repr(u8)]
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pub enum AhciCurrentInterfaceSpeed {
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NoDevice = 0x0,
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Gen1 = 0x1,
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Gen2 = 0x2,
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Gen3 = 0x3,
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Unknown = 0xF,
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}
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impl AhciCurrentInterfaceSpeed {
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoDevice,
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0x1 => Self::Gen1,
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0x2 => Self::Gen2,
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0x3 => Self::Gen3,
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_ => Self::Unknown,
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}
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}
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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pub enum AhciInterfacePowerManagement {
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NoDevice = 0x0,
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Active = 0x1,
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PartialPower = 0x2,
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Slumber = 0x6,
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DevSleep = 0x8,
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Unknown = 0xF,
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}
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impl AhciInterfacePowerManagement {
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoDevice,
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0x1 => Self::Active,
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0x2 => Self::PartialPower,
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0x6 => Self::Slumber,
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0x8 => Self::DevSleep,
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_ => Self::Unknown,
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}
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}
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}
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#[bitfield(u32)]
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#[derive(PartialEq)]
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pub struct AhciSataStatus {
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#[bits(4, access = RO)]
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pub device_detection: AhciDeviceDetection,
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#[bits(4, access = RO)]
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pub current_interface_speed: AhciCurrentInterfaceSpeed,
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#[bits(4, access = RO)]
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pub interface_power_management: AhciInterfacePowerManagement,
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#[bits(20)]
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__: u32,
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}
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#[derive(Debug)]
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#[repr(u8)]
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enum AhciDeviceDetectionInitialization {
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NoDevice = 0x0,
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PerformInterfaceCommunicationInitializationSequence = 0x1,
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DisableSata = 0x4,
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Unknown = 0xF,
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}
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impl AhciDeviceDetectionInitialization {
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const fn into_bits(self) -> u8 {
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self as _
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}
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoDevice,
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0x1 => Self::PerformInterfaceCommunicationInitializationSequence,
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0x4 => Self::DisableSata,
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_ => Self::Unknown,
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}
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}
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}
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#[derive(Debug)]
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#[repr(u8)]
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enum AhciSpeedAllowed {
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NoRestrictions = 0x0,
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LimitGen1 = 0x1,
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LimitGen2 = 0x2,
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LimitGen3 = 0x3,
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Unknown = 0xF,
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}
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impl AhciSpeedAllowed {
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const fn into_bits(self) -> u8 {
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self as _
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}
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const fn from_bits(value: u8) -> Self {
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match value {
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0x0 => Self::NoRestrictions,
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0x1 => Self::LimitGen1,
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0x2 => Self::LimitGen2,
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0x3 => Self::LimitGen3,
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_ => Self::Unknown,
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}
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}
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}
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#[bitfield(u32)]
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pub struct AhciSataControl {
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#[bits(4)]
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device_detection_initialization: AhciDeviceDetectionInitialization,
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#[bits(4)]
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speed_allowed: AhciSpeedAllowed,
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partial_transition_disabled: bool,
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slumber_transition_disabled: bool,
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devsleep_transition_disabled: bool,
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__: bool,
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#[bits(20)]
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__: u32,
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}
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#[bitfield(u32)]
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pub struct AhciSataError {
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pub recovered_data_integrity_error: bool,
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pub recovered_communications_error: bool,
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#[bits(6)]
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__: u8,
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pub transient_data_integrity_error: bool,
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pub persisten_communication_or_data_integrity_error: bool,
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pub protocol_error: bool,
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pub internal_error: bool,
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#[bits(4)]
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__: u8,
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pub phy_ready_change: bool,
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pub phy_internal_error: bool,
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pub comm_wake: bool,
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pub decode_error: bool,
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__: bool,
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pub crc_error: bool,
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pub handshake_error: bool,
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pub link_sequence_error: bool,
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pub transport_state_transition_error: bool,
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pub uknown_fis_type: bool,
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pub exchanged: bool,
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#[bits(5)]
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__: u8,
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}
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#[bitfield(u32)]
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pub struct AhciFisBasedSwitchingControl {
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enable: bool,
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device_error_clear: bool,
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#[bits(access = RO)]
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single_device_error: bool,
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#[bits(5)]
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__: u8,
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#[bits(4)]
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device_to_issue: u8,
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#[bits(4, access = RO)]
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active_device_optimization: u8,
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#[bits(4, access = RO)]
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device_with_error: u8,
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#[bits(12)]
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__: u16,
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}
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#[bitfield(u32)]
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pub struct AhciDeviceSleep {
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aggressive_device_sleep_enable: bool,
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#[bits(access = RO)]
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device_sleep_present: bool,
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device_sleep_exit_timeout: u8,
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#[bits(5)]
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minimum_device_sleep_assertion_time: u8,
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#[bits(10)]
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device_sleep_idle_timeout: u16,
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#[bits(4)]
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dito_multiplier: u8,
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#[bits(3)]
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__: u8,
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}
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#[derive(Debug)]
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#[repr(C, packed)]
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pub struct AhciPortHba {
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pub command_list_base: u64,
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pub fis_base: u64,
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pub interrupt_status: AhciPortInterruptStatus,
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pub interrupt_enable: AhciPortInterruptEnable,
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pub command: AhciPortCommandAndStatus,
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__: u32,
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pub task_file_data: AhciPortTaskFileData,
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pub signature: u32,
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pub sata_status: AhciSataStatus,
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pub sata_control: AhciSataControl,
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pub sata_error: AhciSataError,
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pub sata_active: u32,
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pub command_issue: u32,
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pub sata_notification: u32,
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pub fis_based_switching_ctl: AhciFisBasedSwitchingControl,
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pub device_sleep: AhciDeviceSleep,
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}
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const _: () = assert!(size_of::<AhciPortHba>() == 0x48);
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