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arm: Restrict processor mode change when in hypervisor mode 

If a CPU implements EL2 as its highest exception level then programs
using newlib may start in hypervisor mode.  In that state it is not
trivial to switch into the various EL1 modes to configure the
individual exception stacks, so do not try.
This commit is contained in:
Srinath Parvathaneni 2023-03-03 13:12:18 +00:00 committed by Richard Earnshaw
parent b782dcb2b3
commit 1d3d2ba54b
2 changed files with 14 additions and 14 deletions
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14
libgloss/arm/crt0.S
View File

@ -122,10 +122,10 @@
* +-----+ <- SP_svc of getting in and out of secure state are not as * +-----+ <- SP_svc of getting in and out of secure state are not as
* | | simple as writing to the CPSR mode bits. * | | simple as writing to the CPSR mode bits.
* | IRQ | -= 0x2000 - Mode switch via CPSR is not allowed once in * | IRQ | -= 0x2000 - Mode switch via CPSR is not allowed once in
* | | non-privileged mode, so we take care not to enter * | | non-privileged mode or in hypervisor mode, so we
* ^ +-----+ <- SP_und "User" to set up its SP, and also skip most * ^ +-----+ <- SP_und take care not to enter "User" or "Hypervisor" mode
* s | | operations if already in that mode. * s | | to set up its SP, and also skip most operations if
* t | UND | -= 0x1000 * t | UND | -= 0x1000 already in these modes.
* a | | Input parameters: * a | | Input parameters:
* c +-----+ <- SP_und - sp - Initialized SP * c +-----+ <- SP_und - sp - Initialized SP
* k | | - r2 - May contain SL value from semihosting * k | | - r2 - May contain SL value from semihosting
@ -150,9 +150,9 @@
/* Following code is compatible for both ARM and Thumb ISA. */ /* Following code is compatible for both ARM and Thumb ISA. */
mrs r4, CPSR mrs r4, CPSR
mov r3, sp /* Save input SP value. */ mov r3, sp /* Save input SP value. */
/* Test mode bits - in User of all are 0. */ ands r1, r4, #(CPSR_M_MASK)
tst r4, #(CPSR_M_MASK) beq .Lskip_cpu_modes
/* "eq" means r4 AND #0x0F is 0. */ cmp r1, #(CPSR_M_HYP)
beq .Lskip_cpu_modes beq .Lskip_cpu_modes
/* FIQ mode, interrupts disabled. */ /* FIQ mode, interrupts disabled. */

14
newlib/libc/sys/arm/crt0.S
View File

@ -122,10 +122,10 @@
* +-----+ <- SP_svc of getting in and out of secure state are not as * +-----+ <- SP_svc of getting in and out of secure state are not as
* | | simple as writing to the CPSR mode bits. * | | simple as writing to the CPSR mode bits.
* | IRQ | -= 0x2000 - Mode switch via CPSR is not allowed once in * | IRQ | -= 0x2000 - Mode switch via CPSR is not allowed once in
* | | non-privileged mode, so we take care not to enter * | | non-privileged mode or in hypervisor mode, so we
* ^ +-----+ <- SP_und "User" to set up its SP, and also skip most * ^ +-----+ <- SP_und take care not to enter "User" or "Hypervisor" mode
* s | | operations if already in that mode. * s | | to set up its SP, and also skip most operations if
* t | UND | -= 0x1000 * t | UND | -= 0x1000 already in these modes.
* a | | Input parameters: * a | | Input parameters:
* c +-----+ <- SP_und - sp - Initialized SP * c +-----+ <- SP_und - sp - Initialized SP
* k | | - r2 - May contain SL value from semihosting * k | | - r2 - May contain SL value from semihosting
@ -150,9 +150,9 @@
/* Following code is compatible for both ARM and Thumb ISA. */ /* Following code is compatible for both ARM and Thumb ISA. */
mrs r4, CPSR mrs r4, CPSR
mov r3, sp /* Save input SP value. */ mov r3, sp /* Save input SP value. */
/* Test mode bits - in User of all are 0. */ ands r1, r4, #(CPSR_M_MASK)
tst r4, #(CPSR_M_MASK) beq .Lskip_cpu_modes
/* "eq" means r4 AND #0x0F is 0. */ cmp r1, #(CPSR_M_HYP)
beq .Lskip_cpu_modes beq .Lskip_cpu_modes
/* FIQ mode, interrupts disabled. */ /* FIQ mode, interrupts disabled. */