Specify our target in .ccls

2023-06-16 23:15:41 -07:00 · 2023-06-16 23:15:41 -07:00 · 4c936623b5
parent 35f24e7c77
commit 4c936623b5
2 changed files with 3 additions and 1 deletions
--- a/.ccls
+++ b/.ccls
@ -0,0 +1,2 @@
+%compile_commands.json
+--target=x86_64-pc-acadia-elf
--- a/sys/yellowstone/yellowstone.cpp
+++ b/sys/yellowstone/yellowstone.cpp
@ -6,7 +6,7 @@

 #include "hw/pcie.h"

-int main(uint64_t port_cap) {
+uint64_t main(uint64_t port_cap) {
  dbgln("Yellowstone Initializing.");
  uint64_t msg_type, type, cap, bytes, caps;
  check(ZPortRecv(port_cap, 8, reinterpret_cast<uint8_t*>(&msg_type), 1, &cap,