[Voyageurs] Send AddressDevice Command to move port to 'Addressed' State.
This commit is contained in:
parent
dd2687a59a
commit
8e78950ac7
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@ -1,5 +1,6 @@
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add_executable(voyageurs
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keyboard/keyboard_driver.cpp
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xhci/device_slot.cpp
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xhci/trb.cpp
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xhci/trb_ring.cpp
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xhci/xhci_driver.cpp
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@ -0,0 +1,47 @@
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#include "xhci/device_slot.h"
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#include "xhci/trb.h"
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void DeviceSlot::EnableAndInitializeDataStructures(uint8_t slot_index,
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uint64_t* output_context) {
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enabled_ = true;
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slot_index_ = slot_index;
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context_memory_ =
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mmth::OwnedMemoryRegion::ContiguousPhysical(0x1000, &context_phys_);
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device_context_ =
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reinterpret_cast<XhciDeviceContext*>(context_memory_.vaddr());
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*output_context = context_phys_;
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input_context_ = reinterpret_cast<XhciInputContext*>(context_memory_.vaddr() +
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kInputSlotContextOffset);
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control_endpoint_transfer_trb_ = glcr::MakeUnique<TrbRingWriter>();
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}
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XhciTrb DeviceSlot::CreateAddressDeviceCommand(uint8_t root_port,
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uint32_t route_string,
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uint16_t max_packet_size) {
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// Initialize Slot Context and Endpoint 0 Context.
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input_context_->input.add_contexts = 0x3;
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// Set context_entries to 1. XHCI 4.3.3
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input_context_->slot_context.route_speed_entries = (0x1 << 27) | route_string;
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input_context_->slot_context.latency_port_number = root_port << 16;
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// Initialize Control Endpoint.
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input_context_->endpoint_contexts[0].state = 0;
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constexpr uint16_t kCerr = 0x3 << 1;
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constexpr uint16_t kTypeControl = 0x4 << 3;
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input_context_->endpoint_contexts[0].error_and_type =
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kCerr | kTypeControl | (max_packet_size << 16);
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input_context_->endpoint_contexts[0].tr_dequeue_ptr =
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control_endpoint_transfer_trb_->PhysicalAddress() | 0x1;
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return ::CreateAddressDeviceCommand(context_phys_ + kInputSlotContextOffset,
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slot_index_);
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}
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uint8_t DeviceSlot::State() {
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return device_context_->slot_context.address_and_state >> 27;
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}
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@ -0,0 +1,37 @@
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#pragma once
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#include <glacier/memory/unique_ptr.h>
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#include <mammoth/util/memory_region.h>
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#include "xhci/trb_ring.h"
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#include "xhci/xhci.h"
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class DeviceSlot {
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public:
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DeviceSlot() = default;
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DeviceSlot(const DeviceSlot&) = delete;
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DeviceSlot(DeviceSlot&&) = delete;
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void EnableAndInitializeDataStructures(uint8_t slot_index_,
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uint64_t* output_context);
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XhciTrb CreateAddressDeviceCommand(uint8_t root_port, uint32_t route_string,
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uint16_t max_packet_size);
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uint8_t State();
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private:
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bool enabled_ = false;
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uint8_t slot_index_ = 0;
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uint64_t context_phys_ = 0;
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mmth::OwnedMemoryRegion context_memory_;
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static constexpr uint64_t kInputSlotContextOffset = 0x400;
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XhciDeviceContext* device_context_;
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XhciInputContext* input_context_;
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glcr::UniquePtr<TrbRingWriter> control_endpoint_transfer_trb_;
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};
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@ -1,26 +1,27 @@
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#include "xhci/trb.h"
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constexpr uint8_t kTrb_Normal = 1;
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constexpr uint8_t kTrb_SetupStage = 2;
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constexpr uint8_t kTrb_DataStage = 3;
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constexpr uint8_t kTrb_StatusStage = 4;
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constexpr uint8_t kTrb_Isoch = 5;
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constexpr uint8_t kTrb_Link = 6;
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constexpr uint8_t kTrb_EventData = 7;
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constexpr uint8_t kTrb_NoOp = 8;
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constexpr uint8_t kTrb_EnableSlot = 9;
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constexpr uint8_t kTrb_DisableSlot = 10;
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constexpr uint8_t kTrb_NoOpCommand = 23;
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constexpr uint8_t kTrb_TypeOffset = 10;
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constexpr uint8_t kTrb_Cycle = 1;
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constexpr uint16_t kTrb_Cycle = 1;
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constexpr uint16_t kTrb_BSR = (1 << 9);
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namespace {
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uint16_t TypeToInt(TrbType type) {
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return static_cast<uint16_t>(type) << kTrb_TypeOffset;
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}
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} // namespace
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TrbType GetType(const XhciTrb& trb) {
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return TrbType(trb.type_and_cycle >> kTrb_TypeOffset);
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}
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XhciTrb CreateLinkTrb(uint64_t physical_address) {
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return {
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.parameter = physical_address,
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.status = 0,
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.type_and_cycle = kTrb_Link << kTrb_TypeOffset,
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.type_and_cycle = TypeToInt(TrbType::Link),
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.control = 0,
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};
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}
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@ -30,18 +31,30 @@ XhciTrb CreateEnableSlotTrb() {
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.parameter = 0,
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.status = 0,
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// FIXME: Accept Cycle Bit as a parameter.
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.type_and_cycle = kTrb_EnableSlot << kTrb_TypeOffset | kTrb_Cycle,
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.type_and_cycle = (uint16_t)(TypeToInt(TrbType::EnableSlot) | kTrb_Cycle),
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// FIXME: Specify slot type if necessary. (XHCI Table 7-9)?
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.control = 0,
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};
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}
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XhciTrb CreateAddressDeviceCommand(uint64_t input_context, uint8_t slot_id) {
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return {
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.parameter = input_context,
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.status = 0,
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// Always cycle the device straight to addressed.
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.type_and_cycle =
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(uint16_t)(TypeToInt(TrbType::AddressDevice) | kTrb_Cycle),
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.control = (uint16_t)(slot_id << 8),
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};
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}
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XhciTrb CreateNoOpCommandTrb() {
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return {
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.parameter = 0,
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.status = 0,
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// FIXME: Accept Cycle Bit as a parameter.
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.type_and_cycle = kTrb_NoOpCommand << kTrb_TypeOffset | kTrb_Cycle,
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.type_and_cycle =
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(uint16_t)(TypeToInt(TrbType::NoOpCommand) | kTrb_Cycle),
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.control = 0,
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};
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}
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@ -2,7 +2,33 @@
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#include "xhci/xhci.h"
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enum class TrbType : uint8_t {
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Reserved = 0,
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// Transfers
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Normal = 1,
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SetupStage = 2,
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DataStage = 3,
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StatusStage = 4,
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Isoch = 5,
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Link = 6,
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EventData = 7,
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NoOp = 8,
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// Commands
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EnableSlot = 9,
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AddressDevice = 11,
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NoOpCommand = 23,
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// Events
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CommandCompletion = 33,
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PortStatusChange = 34,
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};
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TrbType GetType(const XhciTrb& trb);
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XhciTrb CreateLinkTrb(uint64_t physical_address);
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XhciTrb CreateEnableSlotTrb();
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XhciTrb CreateAddressDeviceCommand(uint64_t input_context, uint8_t slot_id);
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XhciTrb CreateNoOpCommandTrb();
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@ -20,6 +20,15 @@ TrbRing::TrbRing() {
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trb_list_[trb_list_.size() - 1] = CreateLinkTrb(phys_address_);
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}
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XhciTrb TrbRing::GetTrbFromPhysical(uint64_t address) {
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uint64_t offset = address - phys_address_;
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if (offset >= 0x1000) {
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crash("Invalid offset in GetTrbFromPhysical", glcr::INVALID_ARGUMENT);
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}
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offset /= sizeof(XhciTrb);
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return trb_list_[offset];
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}
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void TrbRingWriter::EnqueueTrb(const XhciTrb& trb) {
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uint64_t ptr = enqueue_ptr_++;
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if (enqueue_ptr_ == trb_list_.size()) {
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@ -10,6 +10,7 @@ class TrbRing {
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TrbRing();
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uint64_t PhysicalAddress() { return phys_address_; }
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XhciTrb GetTrbFromPhysical(uint64_t address);
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protected:
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uint64_t phys_address_;
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@ -43,6 +43,13 @@ struct XhciCapabilities {
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uint32_t capabilities2;
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} __attribute__((packed));
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struct XhciPort {
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uint32_t status_and_control;
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uint32_t power_management;
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uint32_t link_info;
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uint32_t lpm_control;
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} __attribute__((packed));
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struct XhciOperational {
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uint32_t usb_command;
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uint32_t usb_status;
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uint64_t reserved4;
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uint64_t device_context_base;
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uint32_t configure;
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XhciPort ports[255];
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} __attribute__((packed));
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struct XhciInterrupter {
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uint32_t doorbell[256];
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} __attribute__((packed));
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struct XhciPort {
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uint32_t status_and_control;
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uint32_t power_management;
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uint32_t link_info;
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uint32_t lpm_control;
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} __attribute__((packed));
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struct XhciSlotContext {
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uint32_t route_speed_entries;
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uint32_t latency_port_number;
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XhciEndpointContext endpoint_contexts[31];
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} __attribute__((packed));
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struct XhciInputControlContext {
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uint32_t drop_contexts;
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uint32_t add_contexts;
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uint64_t reserved1;
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uint64_t reserved2;
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uint32_t reserved3;
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uint8_t configuration_value;
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uint8_t interface_number;
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uint8_t alternate_setting;
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uint8_t reserved4;
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} __attribute__((packed));
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struct XhciInputContext {
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XhciInputControlContext input;
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XhciSlotContext slot_context;
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XhciEndpointContext endpoint_contexts[31];
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} __attribute__((packed));
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struct XhciTrb {
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uint64_t parameter;
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uint32_t status;
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@ -42,23 +42,18 @@ void XhciDriver::InterruptLoop() {
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}
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while (event_ring_.HasNext()) {
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XhciTrb trb = event_ring_.Read();
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uint16_t type = trb.type_and_cycle >> 10;
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switch (type) {
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case 33:
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dbgln(
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"Command Completion Event. TRB Ptr: {x}, Status: {x}, Param: {x} "
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"Slot ID: {x}",
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trb.parameter, trb.status >> 24, trb.status & 0xFFFFFF,
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trb.control >> 8);
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switch (GetType(trb)) {
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case TrbType::CommandCompletion:
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HandleCommandCompletion(trb);
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break;
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case 34:
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case TrbType::PortStatusChange:
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dbgln("Port Status Change Event on Port {x}, enabling slot.",
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((trb.parameter >> 24) & 0xFF) - 1);
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command_ring_.EnqueueTrb(CreateEnableSlotTrb());
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doorbells_->doorbell[0] = 0;
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break;
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default:
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dbgln("Unknown TRB Type {x} received.", type);
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dbgln("Unknown TRB Type {x} received.", (uint8_t)GetType(trb));
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break;
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}
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}
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@ -125,6 +120,9 @@ glcr::ErrorCode XhciDriver::ParseMmioStructures() {
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capabilities_ = reinterpret_cast<XhciCapabilities*>(mmio_regions_.vaddr());
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uint8_t max_device_slots = capabilities_->hcs_params_1 & 0xFF;
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devices_ = glcr::Array<DeviceSlot>(max_device_slots);
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uint64_t op_base =
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mmio_regions_.vaddr() + (capabilities_->length_and_version & 0xFF);
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operational_ = reinterpret_cast<XhciOperational*>(op_base);
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@ -247,3 +245,47 @@ glcr::ErrorCode XhciDriver::NoOpCommand() {
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doorbells_->doorbell[0] = 0;
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return glcr::OK;
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}
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void XhciDriver::HandleCommandCompletion(
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const XhciTrb& command_completion_trb) {
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uint8_t status = command_completion_trb.status >> 24;
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if (status != 1) {
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dbgln("Command Completion Status: {x}", command_completion_trb.status);
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check(glcr::INTERNAL);
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}
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XhciTrb orig_trb =
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command_ring_.GetTrbFromPhysical(command_completion_trb.parameter);
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uint8_t slot = command_completion_trb.control >> 8;
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switch (GetType(orig_trb)) {
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case TrbType::EnableSlot:
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dbgln("Slot Enabled: {x}", slot);
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InitializeSlot(slot);
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break;
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case TrbType::AddressDevice:
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dbgln("Device Addressed: {x}", slot);
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dbgln("State: {x}", devices_[slot - 1].State());
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break;
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case TrbType::NoOpCommand:
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dbgln("No-op Command Completed");
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break;
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default:
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dbgln("Unhandled Command Completion Type: {x}",
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(uint8_t)(GetType(orig_trb)));
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}
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}
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void XhciDriver::InitializeSlot(uint8_t slot_index) {
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// TODO: Consider making this array one longer and ignore the first value.
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devices_[slot_index - 1].EnableAndInitializeDataStructures(
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slot_index, &(device_context_base_array_[slot_index]));
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XhciPort* port =
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reinterpret_cast<XhciPort*>(reinterpret_cast<uint64_t>(operational_) +
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0x400 + (0x10 * (slot_index - 1)));
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uint8_t port_speed = (port->status_and_control >> 10) & 0xF;
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uint8_t max_packet_size = 8;
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XhciTrb address_device = devices_[slot_index - 1].CreateAddressDeviceCommand(
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0x5, 0, max_packet_size);
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command_ring_.EnqueueTrb(address_device);
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doorbells_->doorbell[0] = 0;
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}
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@ -1,11 +1,13 @@
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#pragma once
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#include <glacier/container/array.h>
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#include <glacier/memory/unique_ptr.h>
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#include <glacier/status/error_or.h>
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#include <mammoth/proc/thread.h>
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#include <mammoth/util/memory_region.h>
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#include <yellowstone/yellowstone.yunq.client.h>
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#include "xhci/device_slot.h"
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#include "xhci/trb_ring.h"
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#include "xhci/xhci.h"
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@ -45,6 +47,8 @@ class XhciDriver {
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TrbRingReader event_ring_;
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Thread interrupt_thread_;
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glcr::Array<DeviceSlot> devices_;
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XhciDriver(mmth::OwnedMemoryRegion&& pci_space);
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glcr::ErrorCode ParseMmioStructures();
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@ -60,4 +64,8 @@ class XhciDriver {
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glcr::ErrorCode InitiateDevices();
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glcr::ErrorCode NoOpCommand();
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void HandleCommandCompletion(const XhciTrb& command_completion_trb);
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void InitializeSlot(uint8_t slot_index);
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};
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