2023-06-12 19:20:51 -07:00
|
|
|
#include "ahci/ahci_device.h"
|
|
|
|
|
2023-06-21 18:28:54 -07:00
|
|
|
#include <glacier/status/error.h>
|
2023-06-12 19:20:51 -07:00
|
|
|
#include <mammoth/debug.h>
|
|
|
|
#include <string.h>
|
|
|
|
#include <zcall.h>
|
|
|
|
|
|
|
|
AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
|
|
|
|
if ((port_struct_->sata_status & 0x103) != 0x103) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2023-07-05 14:32:19 -07:00
|
|
|
// 0x0-0x400 -> Command List
|
|
|
|
// 0x400-0x500 -> Received FIS
|
|
|
|
// 0x500-0x2500 -> Command Tables (0x100 each) (Max PRDT Length is 8 for now)
|
|
|
|
command_structures_ = MappedMemoryRegion::ContiguousPhysical(0x2500);
|
|
|
|
uint64_t paddr = command_structures_.paddr();
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-07-05 14:32:19 -07:00
|
|
|
command_list_ = reinterpret_cast<CommandList*>(command_structures_.vaddr());
|
|
|
|
port_struct_->command_list_base = paddr;
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-06-12 23:32:24 -07:00
|
|
|
received_fis_ =
|
2023-07-05 14:32:19 -07:00
|
|
|
reinterpret_cast<ReceivedFis*>(command_structures_.vaddr() + 0x400);
|
|
|
|
port_struct_->fis_base = paddr + 0x400;
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-07-05 14:32:19 -07:00
|
|
|
command_tables_ =
|
|
|
|
reinterpret_cast<CommandTable*>(command_structures_.vaddr() + 0x500);
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-07-05 14:32:19 -07:00
|
|
|
for (uint64_t i = 0; i < 32; i++) {
|
|
|
|
command_list_->command_headers[i].command_table_base_addr =
|
|
|
|
(paddr + 0x500) + (0x100 * i);
|
|
|
|
}
|
2023-06-12 19:20:51 -07:00
|
|
|
port_struct_->interrupt_enable = 0xFFFFFFFF;
|
2023-07-05 14:32:19 -07:00
|
|
|
// Reset the CMD and FRE bits since we move these structures.
|
|
|
|
// FIXME: I think we need to poll these bits to make sure they become
|
|
|
|
// 0 before setting them back to one.
|
|
|
|
port_struct_->command &= ~(0x00000011);
|
|
|
|
port_struct_->command |= 0x00000011;
|
2023-06-12 19:20:51 -07:00
|
|
|
}
|
|
|
|
|
2023-06-21 18:38:11 -07:00
|
|
|
glcr::ErrorCode AhciDevice::IssueCommand(Command* command) {
|
2023-07-05 14:32:19 -07:00
|
|
|
command->PopulateFis(command_tables_->command_fis);
|
|
|
|
command->PopulatePrdt(command_tables_->prdt);
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-06-16 01:31:23 -07:00
|
|
|
command_list_->command_headers[0].command =
|
|
|
|
(sizeof(HostToDeviceRegisterFis) / 2) & 0x1F;
|
2023-06-12 19:20:51 -07:00
|
|
|
command_list_->command_headers[0].prd_table_length = 1;
|
2023-06-16 01:31:23 -07:00
|
|
|
command_list_->command_headers[0].prd_byte_count = 0;
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-06-16 01:31:23 -07:00
|
|
|
commands_[0] = command;
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-06-12 23:32:24 -07:00
|
|
|
commands_issued_ |= 1;
|
2023-06-16 01:31:23 -07:00
|
|
|
port_struct_->command_issue |= 1;
|
2023-06-12 19:20:51 -07:00
|
|
|
|
2023-06-21 18:28:54 -07:00
|
|
|
return glcr::OK;
|
2023-06-12 19:20:51 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void AhciDevice::DumpInfo() {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("Comlist: {x}", port_struct_->command_list_base);
|
|
|
|
dbgln("FIS: {x}", port_struct_->fis_base);
|
|
|
|
dbgln("Command: {x}", port_struct_->command);
|
|
|
|
dbgln("Signature: {x}", port_struct_->signature);
|
|
|
|
dbgln("SATA status: {x}", port_struct_->sata_status);
|
|
|
|
dbgln("Int status: {x}", port_struct_->interrupt_status);
|
|
|
|
dbgln("Int enable: {x}", port_struct_->interrupt_enable);
|
2023-06-12 19:20:51 -07:00
|
|
|
|
|
|
|
// Just dump one command info for now.
|
2023-07-05 14:32:19 -07:00
|
|
|
for (uint64_t i = 0; i < 32; i++) {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("Command Header: {}", i);
|
|
|
|
dbgln("Command {x}", command_list_->command_headers[i].command);
|
|
|
|
dbgln("PRD Len: {x}", command_list_->command_headers[i].prd_table_length);
|
|
|
|
dbgln("Command Table {x}",
|
2023-06-12 19:20:51 -07:00
|
|
|
command_list_->command_headers[i].command_table_base_addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void AhciDevice::HandleIrq() {
|
2023-07-05 14:32:19 -07:00
|
|
|
uint32_t int_status = port_struct_->interrupt_status;
|
2023-06-12 19:20:51 -07:00
|
|
|
// FIXME: Probably only clear the interrupts we know how to handle.
|
|
|
|
port_struct_->interrupt_status = int_status;
|
|
|
|
|
2023-06-12 23:32:24 -07:00
|
|
|
uint32_t commands_finished = commands_issued_ & ~port_struct_->command_issue;
|
|
|
|
|
2023-06-16 01:31:23 -07:00
|
|
|
// FIXME: Pass error codes to the callback.
|
2023-06-12 23:32:24 -07:00
|
|
|
for (uint64_t i = 0; i < 32; i++) {
|
|
|
|
if (commands_finished & (1 << i)) {
|
|
|
|
commands_issued_ &= ~(1 << i);
|
2023-06-16 01:31:23 -07:00
|
|
|
commands_[i]->Callback();
|
2023-06-12 23:32:24 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// TODO: Do something with this information.
|
|
|
|
if (int_status & 0x1) {
|
|
|
|
// Device to host.
|
|
|
|
DeviceToHostRegisterFis& fis = received_fis_->device_to_host_register_fis;
|
|
|
|
if (fis.fis_type != FIS_TYPE_REG_D2H) {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
|
|
|
|
static_cast<uint64_t>(FIS_TYPE_REG_D2H),
|
|
|
|
static_cast<uint64_t>(fis.fis_type));
|
2023-06-12 23:32:24 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (fis.error) {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("D2H err: {x}", fis.error);
|
|
|
|
dbgln("status: {x}", fis.status);
|
2023-06-12 23:32:24 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (int_status & 0x2) {
|
|
|
|
// PIO.
|
|
|
|
PioSetupFis& fis = received_fis_->pio_set_fis;
|
|
|
|
if (fis.fis_type != FIS_TYPE_PIO_SETUP) {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("BAD FIS TYPE (exp,act): {x}, {x}",
|
|
|
|
static_cast<uint64_t>(FIS_TYPE_PIO_SETUP),
|
|
|
|
static_cast<uint64_t>(fis.fis_type));
|
2023-06-12 23:32:24 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (fis.error) {
|
2023-11-03 02:48:21 -07:00
|
|
|
dbgln("PIO err: {x}", fis.error);
|
2023-06-12 23:32:24 -07:00
|
|
|
}
|
|
|
|
}
|
2023-06-12 19:20:51 -07:00
|
|
|
}
|